Loading arch/arm/mach-msm/timer.c +11 −3 Original line number Diff line number Diff line Loading @@ -23,6 +23,8 @@ #include <linux/io.h> #include <asm/mach/time.h> #include <asm/hardware/gic.h> #include <mach/msm_iomap.h> #include <mach/cpu.h> Loading Loading @@ -55,10 +57,12 @@ enum timer_location { #if defined(CONFIG_ARCH_QSD8X50) #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */ #define MSM_DGT_SHIFT (0) #elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \ defined(CONFIG_ARCH_MSM8960) #elif defined(CONFIG_ARCH_MSM7X30) #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */ #define MSM_DGT_SHIFT (0) #elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960) #define DGT_HZ (27000000 / 4) /* 27 MHz (PXO) / 4 by default */ #define MSM_DGT_SHIFT (0) #else #define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */ #define MSM_DGT_SHIFT (5) Loading Loading @@ -100,7 +104,11 @@ static cycle_t msm_read_timer_count(struct clocksource *cs) { struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource); return readl(clk->global_counter); /* * Shift timer count down by a constant due to unreliable lower bits * on some targets. */ return readl(clk->global_counter) >> clk->shift; } static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt) Loading Loading
arch/arm/mach-msm/timer.c +11 −3 Original line number Diff line number Diff line Loading @@ -23,6 +23,8 @@ #include <linux/io.h> #include <asm/mach/time.h> #include <asm/hardware/gic.h> #include <mach/msm_iomap.h> #include <mach/cpu.h> Loading Loading @@ -55,10 +57,12 @@ enum timer_location { #if defined(CONFIG_ARCH_QSD8X50) #define DGT_HZ (19200000 / 4) /* 19.2 MHz / 4 by default */ #define MSM_DGT_SHIFT (0) #elif defined(CONFIG_ARCH_MSM7X30) || defined(CONFIG_ARCH_MSM8X60) || \ defined(CONFIG_ARCH_MSM8960) #elif defined(CONFIG_ARCH_MSM7X30) #define DGT_HZ (24576000 / 4) /* 24.576 MHz (LPXO) / 4 by default */ #define MSM_DGT_SHIFT (0) #elif defined(CONFIG_ARCH_MSM8X60) || defined(CONFIG_ARCH_MSM8960) #define DGT_HZ (27000000 / 4) /* 27 MHz (PXO) / 4 by default */ #define MSM_DGT_SHIFT (0) #else #define DGT_HZ 19200000 /* 19.2 MHz or 600 KHz after shift */ #define MSM_DGT_SHIFT (5) Loading Loading @@ -100,7 +104,11 @@ static cycle_t msm_read_timer_count(struct clocksource *cs) { struct msm_clock *clk = container_of(cs, struct msm_clock, clocksource); return readl(clk->global_counter); /* * Shift timer count down by a constant due to unreliable lower bits * on some targets. */ return readl(clk->global_counter) >> clk->shift; } static struct msm_clock *clockevent_to_clock(struct clock_event_device *evt) Loading