Commit 85c4ae5d authored by Jie Wang's avatar Jie Wang Committed by Jiantao Xiao
Browse files

net: hns3: add 5ms delay before clear firmware reset irq source 

mainline inclusion
from mainline-v6.6-rc3
commit 07700630
category: bugfix
bugzilla: https://gitee.com/openeuler/kernel/issues/I83ZCY
CVE: NA

Reference: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=0770063096d5da4a8e467b6e73c1646a75589628



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Currently the reset process in hns3 and firmware watchdog init process is
asynchronous. we think firmware watchdog initialization is completed
before hns3 clear the firmware interrupt source. However, firmware
initialization may not complete early.

so we add delay before hns3 clear firmware interrupt source and 5 ms delay
is enough to avoid second firmware reset interrupt.

Fixes: c1a81619 ("net: hns3: Add mailbox interrupt handling to PF driver")
Signed-off-by: default avatarJie Wang <wangjie125@huawei.com>
Signed-off-by: default avatarJijie Shao <shaojijie@huawei.com>
Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
Signed-off-by: default avatarJiantao Xiao <xiaojiantao1@h-partners.com>
parent 753c521f

drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.c

+5 −0
Original line number Diff line number Diff line
@@ -3469,9 +3469,14 @@ static u32 hclge_check_event_cause(struct hclge_dev *hdev, u32 *clearval) 
static void hclge_clear_event_cause(struct hclge_dev *hdev, u32 event_type,

				    u32 regclr)

{

#define HCLGE_IMP_RESET_DELAY		5



	switch (event_type) {

	case HCLGE_VECTOR0_EVENT_PTP:

	case HCLGE_VECTOR0_EVENT_RST:

		if (regclr == BIT(HCLGE_VECTOR0_IMPRESET_INT_B))

			mdelay(HCLGE_IMP_RESET_DELAY);



		hclge_write_dev(&hdev->hw, HCLGE_MISC_RESET_STS_REG, regclr);

		break;

	case HCLGE_VECTOR0_EVENT_MBX: