Commit 85b1d7b3 authored by Jesse Barnes's avatar Jesse Barnes Committed by Daniel Vetter
Browse files

drm/i915: move VLV DDR freq fetch into init_clock_gating 



We don't want it delayed with the RPS work.

Signed-off-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent f3419158

drivers/gpu/drm/i915/intel_pm.c

+18 −13
Original line number Diff line number Diff line
@@ -4064,19 +4064,6 @@ static void valleyview_enable_rps(struct drm_device *dev) 
	I915_WRITE(GEN6_RC_CONTROL, rc6_mode);



	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

	switch ((val >> 6) & 3) {

	case 0:

	case 1:

		dev_priv->mem_freq = 800;

		break;

	case 2:

		dev_priv->mem_freq = 1066;

		break;

	case 3:

		dev_priv->mem_freq = 1333;

		break;

	}

	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);



	DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");

	DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
@@ -5325,6 +5312,24 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) 
static void valleyview_init_clock_gating(struct drm_device *dev)

{

	struct drm_i915_private *dev_priv = dev->dev_private;

	u32 val;



	mutex_lock(&dev_priv->rps.hw_lock);

	val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);

	mutex_unlock(&dev_priv->rps.hw_lock);

	switch ((val >> 6) & 3) {

	case 0:

	case 1:

		dev_priv->mem_freq = 800;

		break;

	case 2:

		dev_priv->mem_freq = 1066;

		break;

	case 3:

		dev_priv->mem_freq = 1333;

		break;

	}

	DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);



	I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);