Commit 85a5f963 authored by Naveen Mamindlapalli's avatar Naveen Mamindlapalli Committed by David S. Miller
Browse files

octeontx2-af: Initialize PTP_SEC_ROLLOVER register properly 



Since the reset value of PTP_SEC_ROLLOVER is incorrect on
CNF10KB silicon, the ptp timestamps are inaccurate. This
patch initializes the PTP_SEC_ROLLOVER register properly
for the CNF10KB silicon.

Signed-off-by: default avatarNaveen Mamindlapalli <naveenm@marvell.com>
Signed-off-by: default avatarSunil Kovvuri Goutham <sgoutham@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 2ef4e45d

drivers/net/ethernet/marvell/octeontx2/af/ptp.c

+10 −0
Original line number Diff line number Diff line
@@ -52,12 +52,18 @@ 
#define PTP_CLOCK_COMP				0xF18ULL

#define PTP_TIMESTAMP				0xF20ULL

#define PTP_CLOCK_SEC				0xFD0ULL

#define PTP_SEC_ROLLOVER			0xFD8ULL



#define CYCLE_MULT				1000



static struct ptp *first_ptp_block;

static const struct pci_device_id ptp_id_table[];



static bool is_ptp_dev_cnf10kb(struct ptp *ptp)

{

	return (ptp->pdev->subsystem_device == PCI_SUBSYS_DEVID_CNF10K_B_PTP) ? true : false;

}



static bool is_ptp_dev_cn10k(struct ptp *ptp)

{

	return (ptp->pdev->device == PCI_DEVID_CN10K_PTP) ? true : false;
@@ -290,6 +296,10 @@ void ptp_start(struct ptp *ptp, u64 sclk, u32 ext_clk_freq, u32 extts) 
	/* sclk is in MHz */

	ptp->clock_rate = sclk * 1000000;



	/* Program the seconds rollover value to 1 second */

	if (is_ptp_dev_cnf10kb(ptp))

		writeq(0x3b9aca00, ptp->reg_base + PTP_SEC_ROLLOVER);



	/* Enable PTP clock */

	clock_cfg = readq(ptp->reg_base + PTP_CLOCK_CFG);