Commit 859161b9 authored by Stanislav Lisovskiy's avatar Stanislav Lisovskiy
Browse files

drm/i915/dg2: Bump up CDCLK for DG2 



We seem to need this W/A same way as for TGL, in order
to fix some of the underruns, which we currently have and
those not related to PSR.

Signed-off-by: default avatarStanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: default avatarUma Shankar <uma.shankar@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220614123049.16183-2-stanislav.lisovskiy@intel.com
parent 3d9c653c

drivers/gpu/drm/i915/display/intel_cdclk.c

+2 −2
Original line number Diff line number Diff line
@@ -2300,7 +2300,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 
		min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);



	/*

	 * HACK. Currently for TGL platforms we calculate

	 * HACK. Currently for TGL/DG2 platforms we calculate

	 * min_cdclk initially based on pixel_rate divided

	 * by 2, accounting for also plane requirements,

	 * however in some cases the lowest possible CDCLK
@@ -2308,7 +2308,7 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state) 
	 * Explicitly stating here that this seems to be currently

	 * rather a Hack, than final solution.

	 */

	if (IS_TIGERLAKE(dev_priv)) {

	if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) {

		/*

		 * Clamp to max_cdclk_freq in case pixel rate is higher,

		 * in order not to break an 8K, but still leave W/A at place.