Commit 84e12236 authored by Yizhen Fan's avatar Yizhen Fan
Browse files

ub: add new feature for urma 

driver inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I8HQP7


CVE: NA

------------------------------------------------

The UB feature has evolved. The UB protocol has been optimized and the
URMA feature has been added to support the UB hardware. The following
features are added:

- Device management
Configuring the EID and UPI
Supports device source IP address management, UBoE MAC address, and VLAN.
Function hot swap

- Supports TP link setup management.
Creating and deleting TPs of the RM, RC, and UM types
The following TP parameters can be configured:
MTU, out-of-order reception, TP retransmission times and timeout,
congestion algorithm and parameters, selective retransmission, DSCP, PSN,
UDP port number, hop_limit,
spray_en, DCA (Dynamic Connection Management)"
Supports destination IP address management and UBoE destination MAC
address and VLAN query and configuration.
TP fault handling

- TPG management
TPGs can be created and deleted. TP attributes in a TPG can be updated.

- Jetty management
The suspend mode of Jetty and jfs is supported.
The flush jetty and jfs functions are supported.
The Jetty, JFS, and JFR attributes or status can be queried.
The Jetty and jfs status can be modified.
The Jetty and JFR thresholds and watermarks can be modified.
RC tables can be created and deleted.

- Supports Jetty groups.
Jetty groups can be created and deleted. Importing and Unimporting Jetty
Groups
Creating and Deleting a Jetty in a Jetty Group
The jetty group can be used to perform operations on the data plane.

- Supports segment security management.
Allocates and releases token IDs, and supports kernel-mode and user-mode
permissions.
Supports the segment security mechanism.

- VPC information can be configured on OpenStack.
Supports VM EID configuration and management.
Supports VM UB device management.

- Supports gaea connect.
Supports gaea hook framework connect.

- Create and delete VTPs, manage VTPs, and configure the mapping between
VTPs and TPs, TPGs, or UTPs (DIPs) to drivers.
Creates and deletes VTPs, and configures the mapping between VTPs and TPs,
TPGs, or UTPs (DIPs) to drivers.
The UVS/UBCore supports VTP table management, including initializing the
 VTP table and adding and deleting VTP entries.

- Supports the UVS dynamic library and UVS servitization.
Supports the UVS dynamic library (running in the Gaea process).
Supports the UVS daemon process and UVS admin process.

- Kernel-mode and user-mode VTP resources and DFX such as RC tables,
Kernel-mode and user-mode VTP resource DFX
RC table DFX

Signed-off-by: default avatarGuoxin Qian <qianguoxin@huawei.com>
Signed-off-by: default avatarYizhen Fan <fanyizhen@huawei.com>
Signed-off-by: default avatarChunzhi Hu <huchunzhi@huawei.com>
parent 7188c2d1

drivers/ub/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -2,7 +2,7 @@ 


menuconfig UB

	tristate "Unified Bus (UB) core support"

	depends on ARM64 || X86_64 || COMPILE_TEST

	depends on ARM64 || X86_64

	default n

	help

	  Core support for Unified Bus (UB).

drivers/ub/hw/hns3/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -12,6 +12,6 @@ $(MODULE_NAME)-objs := hns3_udma_hw.o hns3_udma_main.o hns3_udma_cmd.o \ 
			hns3_udma_db.o hns3_udma_jfc.o hns3_udma_jfr.o \

			hns3_udma_segment.o  hns3_udma_tp.o hns3_udma_jfs.o \

			hns3_udma_jetty.o hns3_udma_sysfs.o hns3_udma_dca.o \

			hns3_udma_dfx.o

			hns3_udma_dfx.o hns3_udma_eid.o



obj-$(CONFIG_UB_UDMA_HNS3) := hns3_udma.o

drivers/ub/hw/hns3/hns3_udma_cmd.c

+3 −1
Original line number Diff line number Diff line
@@ -161,6 +161,7 @@ static uint32_t udma_cmd_hw_resetting(struct udma_dev *dev, 
	ret = read_poll_timeout_atomic(ops->ae_dev_reset_cnt, val,

				       val > dev->reset_cnt, HW_RESET_DELAY_US,

				       HW_RESET_TIMEOUT_US, false, handle);

	cond_resched();

	if (!ret)

		dev->is_reset = true;
@@ -298,10 +299,11 @@ static int __udma_cmq_send(struct udma_dev *dev, struct udma_cmq_desc *desc, 
	int ret = 0;

	int i;



	tail = csq->head;



	mutex_lock(&csq->lock);



	tail = csq->head;



	for (i = 0; i < num; i++) {

		csq->desc[csq->head++] = desc[i];

		if (csq->head == csq->desc_num)

drivers/ub/hw/hns3/hns3_udma_cmd.h

+1 −0
Original line number Diff line number Diff line
@@ -101,6 +101,7 @@ enum { 
	UDMA_CMD_DESTROY_CEQC		= 0x93,



	/* SCC CTX BT commands */

	UDMA_CMD_QUERY_SCCC		= 0xa2,

	UDMA_CMD_READ_SCCC_BT0		= 0xa4,

	UDMA_CMD_WRITE_SCCC_BT0		= 0xa5,

drivers/ub/hw/hns3/hns3_udma_device.h

+9 −4
Original line number Diff line number Diff line
@@ -61,6 +61,8 @@ 
#define UDMA_HOP_NUM_0				0xff

#define UDMA_CAP_FLAGS_EX_SHIFT			12



#define UDMA_MAX_EID_NUM			1024



#define UDMA_CMQ_TX_TIMEOUT			30000

#define UDMA_CMQ_DESC_NUM_S			3

#define UDMA_CMD_CSQ_DESC_NUM			1024
@@ -76,6 +78,8 @@ 
#define UDMA_MAX_BT_REGION			3

#define UDMA_MAX_BT_LEVEL			3



#define CQ_BANKID_MASK GENMASK(1, 0)



#define CQC_FIELD_LOC(h, l) ((uint64_t)(h) << 32 | (l))



#define CQC_CQE_BA_L_OFFSET 3
@@ -430,6 +434,7 @@ struct udma_ucontext { 
	uint64_t			pdn;

	struct udma_dca_ctx		dca_ctx;

	void				*dca_dbgfs;

	uint32_t			eid_index;

};



struct udma_cmd_context {
@@ -544,7 +549,6 @@ struct udma_hw { 
	int (*clear_hem)(struct udma_dev *udma_dev,

			 struct udma_hem_table *table, int obj,

			 int step_idx);

	int (*set_eid)(struct udma_dev *udma_dev, union ubcore_eid eid);

	int (*init_eq)(struct udma_dev *udma_dev);

	void (*cleanup_eq)(struct udma_dev *udma_dev);

};
@@ -552,7 +556,6 @@ struct udma_hw { 
struct udma_caps {

	uint64_t		fw_ver;

	uint8_t			num_ports;

	int			gid_table_len[UDMA_MAX_PORTS];

	int			pkey_table_len[UDMA_MAX_PORTS];

	int			local_ca_ack_delay;

	int			num_uars;
@@ -696,6 +699,7 @@ struct udma_caps { 
	uint32_t		num_jetty_shift;

	uint8_t			poe_ch_num;

	uint32_t		speed;

	uint32_t		max_eid_cnt;

};



struct udma_idx_table {
@@ -819,7 +823,6 @@ struct udma_dev { 
	int				irq[UDMA_MAX_IRQ_NUM];

	const char			*irq_names[UDMA_MAX_IRQ_NUM];

	char				dev_name[UBCORE_MAX_DEV_NAME];

	uint64_t			sys_image_guid;

	struct udma_cmdq		cmd;

	int				cmd_mod;

	struct page			*reset_page; /* store reset state */
@@ -842,6 +845,7 @@ struct udma_dev { 
	struct udma_hem_table		qpc_timer_table;

	struct udma_hem_table		cqc_timer_table;

	struct udma_hem_table		gmv_table;

	struct xarray			eid_table;

	uint64_t			dwqe_page;

	uint64_t			dfx_cnt[UDMA_DFX_EQ_TOTAL];

	struct list_head		qp_list;
@@ -862,6 +866,7 @@ struct udma_seg { 
	uint32_t		pbl_hop_num;

	struct udma_mtr		pbl_mtr;

	uint32_t		npages;

	struct udma_ucontext	*ctx;

};



static inline void *udma_buf_offset(struct udma_buf *buf,
@@ -895,7 +900,7 @@ static inline struct udma_ucontext 
	return container_of(uctx, struct udma_ucontext, uctx);

}



static inline struct udma_dev *to_udma_dev(const struct ubcore_device *ubcore_dev)

static inline struct udma_dev *to_udma_dev(struct ubcore_device *ubcore_dev)

{

	return container_of(ubcore_dev, struct udma_dev, ub_dev);

}