Commit 849cc9bd authored by James Morse's avatar James Morse Committed by Will Deacon
Browse files

arm64/sysreg: Convert ID_ISAR4_EL1 to automatic generation 



Convert ID_ISAR4_EL1 to be automatically generated as per DDI0487I.a,
no functional changes.

Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Signed-off-by: default avatarJames Morse <james.morse@arm.com>
Link: https://lore.kernel.org/r/20221130171637.718182-27-james.morse@arm.com


Signed-off-by: default avatarWill Deacon <will@kernel.org>
parent d07016c9

arch/arm64/include/asm/sysreg.h

+0 −10
Original line number Diff line number Diff line
@@ -173,7 +173,6 @@ 
#define SYS_ID_AFR0_EL1			sys_reg(3, 0, 0, 1, 3)

#define SYS_ID_MMFR5_EL1		sys_reg(3, 0, 0, 3, 6)



#define SYS_ID_ISAR4_EL1		sys_reg(3, 0, 0, 2, 4)

#define SYS_ID_ISAR5_EL1		sys_reg(3, 0, 0, 2, 5)

#define SYS_ID_ISAR6_EL1		sys_reg(3, 0, 0, 2, 7)
@@ -688,15 +687,6 @@ 
#define ID_DFR0_EL1_PerfMon_PMUv3p4		0x5

#define ID_DFR0_EL1_PerfMon_PMUv3p5		0x6



#define ID_ISAR4_EL1_SWP_frac_SHIFT		28

#define ID_ISAR4_EL1_PSR_M_SHIFT		24

#define ID_ISAR4_EL1_SynchPrim_frac_SHIFT	20

#define ID_ISAR4_EL1_Barrier_SHIFT		16

#define ID_ISAR4_EL1_SMC_SHIFT			12

#define ID_ISAR4_EL1_Writeback_SHIFT		8

#define ID_ISAR4_EL1_WithShifts_SHIFT		4

#define ID_ISAR4_EL1_Unpriv_SHIFT		0



#define ID_DFR1_EL1_MTPMU_SHIFT		0



#define ID_ISAR5_EL1_RDM_SHIFT		24

arch/arm64/tools/sysreg

+39 −0
Original line number Diff line number Diff line
@@ -382,6 +382,45 @@ Enum 3:0 Saturate 
EndEnum

EndSysreg



Sysreg ID_ISAR4_EL1	3	0	0	2	4

Res0	63:32

Enum	31:28	SWP_frac

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	27:24	PSR_M

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	23:20	SynchPrim_frac

	0b0000	NI

	0b0011	IMP

EndEnum

Enum	19:16	Barrier

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	15:12	SMC

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	11:8	Writeback

	0b0000	NI

	0b0001	IMP

EndEnum

Enum	7:4	WithShifts

	0b0000	NI

	0b0001	LSL3

	0b0011	LS

	0b0100	REG

EndEnum

Enum	3:0	Unpriv

	0b0000	NI

	0b0001	REG_BYTE

	0b0010	SIGNED_HALFWORD

EndEnum

EndSysreg



Sysreg ID_MMFR4_EL1	3	0	0	2	6

Res0	63:32

Enum	31:28	EVT