Unverified Commit 847603c2 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!10184 [RoCE]从社区回合patch到openEuler（OLK-5.10） 

Merge Pull Request from: @cxh269 
 
Add the following patches
        Chengchang Tang (5):
        RDMA/hns: Fix missing pagesize and alignment check in FRMR
        RDMA/hns: Fix shift-out-bounds when max_inline_data is 0
        RDMA/hns: Fix undifined behavior caused by invalid max_sge
        RDMA/hns: Fix insufficient extend DB for VFs.
        RDMA/hns: Fix mbx timing out before CMD execution is completed
        
        Junxian Huang (2):
        RDMA/hns: Check atomic wr length
        RDMA/hns: Fix unmatch exception handling when init eq table fails

https://gitee.com/openeuler/kernel/issues/IADZY7 
 
Link:https://gitee.com/openeuler/kernel/pulls/10184

 

Reviewed-by: default avatarChengchang Tang <tangchengchang@huawei.com>
Signed-off-by: default avatarYang Yingliang <yangyingliang@huawei.com>
parents 14d2851f 9405e506

drivers/infiniband/hw/hns/hns_roce_device.h

+4 −0
Original line number Diff line number Diff line
@@ -88,6 +88,7 @@ 
#define MR_TYPE_DMA				0x03



#define HNS_ROCE_FRMR_MAX_PA			512

#define HNS_ROCE_FRMR_ALIGN_SIZE		128



#define PKEY_ID					0xffff

#define NODE_DESC_SIZE				64
@@ -214,6 +215,9 @@ enum { 
#define HNS_HW_PAGE_SHIFT			12

#define HNS_HW_PAGE_SIZE			(1 << HNS_HW_PAGE_SHIFT)



#define HNS_HW_MAX_PAGE_SHIFT			27

#define HNS_HW_MAX_PAGE_SIZE			(1 << HNS_HW_MAX_PAGE_SHIFT)



struct hns_roce_uar {

	u64		pfn;

	unsigned long	index;

drivers/infiniband/hw/hns/hns_roce_hw_v2.c

+52 −24
Original line number Diff line number Diff line
@@ -693,13 +693,17 @@ static inline int set_rc_wqe(struct hns_roce_qp *qp, 
		     (wr->send_flags & IB_SEND_SIGNALED) ? 1 : 0);



	if (wr->opcode == IB_WR_ATOMIC_CMP_AND_SWP ||

	    wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD)

	    wr->opcode == IB_WR_ATOMIC_FETCH_AND_ADD) {

		if (msg_len != ATOMIC_WR_LEN)

			return -EINVAL;

		ret = set_atomic_seg(hr_dev, wr, rc_sq_wqe, valid_num_sge,

				     msg_len);

	else if (wr->opcode != IB_WR_REG_MR)

	} else if (wr->opcode != IB_WR_REG_MR) {

		ret = set_rwqe_data_seg(&qp->ibqp, wr, rc_sq_wqe,

					&curr_idx, valid_num_sge);



		if (ret)

			return ret;

	}

	if (qp->en_flags & HNS_ROCE_QP_CAP_DYNAMIC_CTX_ATTACH)

		fill_dca_fields(qp, rc_sq_wqe);
@@ -1385,12 +1389,38 @@ static int hns_roce_cmd_err_convert_errno(u16 desc_ret) 
	return -EIO;

}



static u32 hns_roce_cmdq_tx_timeout(u16 opcode, u32 tx_timeout)

{

	static const struct hns_roce_cmdq_tx_timeout_map cmdq_tx_timeout[] = {

		{HNS_ROCE_OPC_POST_MB, HNS_ROCE_OPC_POST_MB_TIMEOUT},

	};

	int i;



	for (i = 0; i < ARRAY_SIZE(cmdq_tx_timeout); i++)

		if (cmdq_tx_timeout[i].opcode == opcode)

			return cmdq_tx_timeout[i].tx_timeout;



	return tx_timeout;

}



static void hns_roce_wait_csq_done(struct hns_roce_dev *hr_dev, u16 opcode)

{

	struct hns_roce_v2_priv *priv = hr_dev->priv;

	u32 tx_timeout = hns_roce_cmdq_tx_timeout(opcode, priv->cmq.tx_timeout);

	u32 timeout = 0;



	do {

		if (hns_roce_cmq_csq_done(hr_dev))

			break;

		udelay(1);

	} while (++timeout < tx_timeout);

}



static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev,

			       struct hns_roce_cmq_desc *desc, int num)

{

	struct hns_roce_v2_priv *priv = hr_dev->priv;

	struct hns_roce_v2_cmq_ring *csq = &priv->cmq.csq;

	u32 timeout = 0;

	u16 desc_ret;

	u32 tail;

	int ret;
@@ -1411,12 +1441,7 @@ static int __hns_roce_cmq_send(struct hns_roce_dev *hr_dev, 


	atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_CMDS_CNT]);



	do {

		if (hns_roce_cmq_csq_done(hr_dev))

			break;

		udelay(1);

	} while (++timeout < priv->cmq.tx_timeout);



	hns_roce_wait_csq_done(hr_dev, le16_to_cpu(desc->opcode));

	if (hns_roce_cmq_csq_done(hr_dev)) {

		ret = 0;

		for (i = 0; i < num; i++) {
@@ -2801,14 +2826,16 @@ static int set_llm_cfg_to_hw(struct hns_roce_dev *hr_dev, 
static struct hns_roce_link_table *

alloc_link_table_buf(struct hns_roce_dev *hr_dev)

{

	u16 total_sl = hr_dev->caps.sl_num * hr_dev->func_num;

	struct hns_roce_v2_priv *priv = hr_dev->priv;

	struct hns_roce_link_table *link_tbl;

	u32 pg_shift, size, min_size;



	link_tbl = &priv->ext_llm;

	pg_shift = hr_dev->caps.llm_buf_pg_sz + PAGE_SHIFT;

	size = hr_dev->caps.num_qps * HNS_ROCE_V2_EXT_LLM_ENTRY_SZ;

	min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(hr_dev->caps.sl_num) << pg_shift;

	size = hr_dev->caps.num_qps * hr_dev->func_num *

	       HNS_ROCE_V2_EXT_LLM_ENTRY_SZ;

	min_size = HNS_ROCE_EXT_LLM_MIN_PAGES(total_sl) << pg_shift;



	/* Alloc data table */

	size = max(size, min_size);
@@ -6984,9 +7011,16 @@ static void hns_roce_v2_int_mask_enable(struct hns_roce_dev *hr_dev, 
	roce_write(hr_dev, ROCEE_VF_ABN_INT_CFG_REG, enable_flag);

}



static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn)

static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)

{

	hns_roce_mtr_destroy(hr_dev, &eq->mtr);

}



static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev,

				    struct hns_roce_eq *eq)

{

	struct device *dev = hr_dev->dev;

	int eqn = eq->eqn;

	int ret;

	u8 cmd;
@@ -6997,12 +7031,9 @@ static void hns_roce_v2_destroy_eqc(struct hns_roce_dev *hr_dev, u32 eqn) 


	ret = hns_roce_destroy_hw_ctx(hr_dev, cmd, eqn & HNS_ROCE_V2_EQN_M);

	if (ret)

		dev_err(dev, "[mailbox cmd] destroy eqc(%u) failed.\n", eqn);

}

		dev_err(dev, "[mailbox cmd] destroy eqc(%d) failed.\n", eqn);



static void free_eq_buf(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)

{

	hns_roce_mtr_destroy(hr_dev, &eq->mtr);

	free_eq_buf(hr_dev, eq);

}



static void init_eq_config(struct hns_roce_dev *hr_dev, struct hns_roce_eq *eq)
@@ -7311,7 +7342,7 @@ static int hns_roce_v2_init_eq_table(struct hns_roce_dev *hr_dev) 


err_create_eq_fail:

	for (i -= 1; i >= 0; i--)

		free_eq_buf(hr_dev, &eq_table->eq[i]);

		hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]);

	kfree(eq_table->eq);



	return ret;
@@ -7331,11 +7362,8 @@ static void hns_roce_v2_cleanup_eq_table(struct hns_roce_dev *hr_dev) 
	__hns_roce_free_irq(hr_dev);

	destroy_workqueue(hr_dev->irq_workq);



	for (i = 0; i < eq_num; i++) {

		hns_roce_v2_destroy_eqc(hr_dev, i);



		free_eq_buf(hr_dev, &eq_table->eq[i]);

	}

	for (i = 0; i < eq_num; i++)

		hns_roce_v2_destroy_eqc(hr_dev, &eq_table->eq[i]);



	kfree(eq_table->eq);

}

drivers/infiniband/hw/hns/hns_roce_hw_v2.h

+6 −0
Original line number Diff line number Diff line
@@ -236,6 +236,12 @@ enum hns_roce_opcode_type { 
	HNS_ROCE_OPC_CHANGE_ACTIVE_PORT			= 0x8603,

};



#define HNS_ROCE_OPC_POST_MB_TIMEOUT 35000

struct hns_roce_cmdq_tx_timeout_map {

	u16 opcode;

	u32 tx_timeout;

};



enum {

	TYPE_CRQ,

	TYPE_CSQ,

drivers/infiniband/hw/hns/hns_roce_mr.c

+5 −0
Original line number Diff line number Diff line
@@ -454,6 +454,11 @@ int hns_roce_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 
	struct hns_roce_mtr *mtr = &mr->pbl_mtr;

	int ret, sg_num = 0;



	if (!IS_ALIGNED(*sg_offset, HNS_ROCE_FRMR_ALIGN_SIZE) ||

	    ibmr->page_size < HNS_HW_PAGE_SIZE ||

	    ibmr->page_size > HNS_HW_MAX_PAGE_SIZE)

		return sg_num;



	mr->npages = 0;

	mr->page_list = kvcalloc(mr->pbl_mtr.hem_cfg.buf_pg_count,

				 sizeof(dma_addr_t), GFP_KERNEL);

drivers/infiniband/hw/hns/hns_roce_qp.c

+2 −1
Original line number Diff line number Diff line
@@ -544,7 +544,8 @@ static unsigned int get_sge_num_from_max_inl_data(bool is_ud_or_gsi, 
						  u32 max_inline_data)

{

	unsigned int inline_sge;



	if (!max_inline_data)

		return 0;

	/*

	 * if max_inline_data less than

	 * HNS_ROCE_SGE_IN_WQE * HNS_ROCE_SGE_SIZE,