Commit 846b73a4 authored by Amit Daniel Kachhap's avatar Amit Daniel Kachhap Committed by Catalin Marinas
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arm64: Add compat hwcap FPHP and ASIMDHP 



These hwcaps were added earlier for 32-bit native arm kernel by commit
c00a19c8 ("ARM: 9268/1: vfp: Add hwcap FPHP and ASIMDHP for FEAT_FP16")
and hence the corresponding changes added in 32-bit compat arm64 kernel for
similar userspace interfaces.

Floating point half-precision (FPHP) and Advanced SIMD half-precision
(ASIMDHP) represents the Armv8 FP16 feature extension and is already
advertised in native arm64 kernel.

Signed-off-by: default avatarAmit Daniel Kachhap <amit.kachhap@arm.com>
Reviewed-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20230111053706.13994-2-amit.kachhap@arm.com


Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent b7bfaa76

arch/arm64/include/asm/hwcap.h

+2 −0
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ 
#define COMPAT_HWCAP_VFPD32	(1 << 19)

#define COMPAT_HWCAP_LPAE	(1 << 20)

#define COMPAT_HWCAP_EVTSTRM	(1 << 21)

#define COMPAT_HWCAP_FPHP	(1 << 22)

#define COMPAT_HWCAP_ASIMDHP	(1 << 23)



#define COMPAT_HWCAP2_AES	(1 << 0)

#define COMPAT_HWCAP2_PMULL	(1 << 1)

arch/arm64/kernel/cpufeature.c

+4 −2
Original line number Diff line number Diff line
@@ -444,8 +444,8 @@ static const struct arm64_ftr_bits ftr_mvfr0[] = { 


static const struct arm64_ftr_bits ftr_mvfr1[] = {

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDFMAC_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_FPHP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDHP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDSP_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDInt_SHIFT, 4, 0),

	ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, MVFR1_EL1_SIMDLS_SHIFT, 4, 0),
@@ -2866,6 +2866,8 @@ static const struct arm64_cpu_capabilities compat_elf_hwcaps[] = { 
	/* Arm v8 mandates MVFR0.FPDP == {0, 2}. So, piggy back on this for the presence of VFP support */

	HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_EL1_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFP),

	HWCAP_CAP(SYS_MVFR0_EL1, MVFR0_EL1_FPDP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_VFPv3),

	HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_EL1_FPHP_SHIFT, 4, FTR_UNSIGNED, 3, CAP_COMPAT_HWCAP, COMPAT_HWCAP_FPHP),

	HWCAP_CAP(SYS_MVFR1_EL1, MVFR1_EL1_SIMDHP_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP, COMPAT_HWCAP_ASIMDHP),

	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_PMULL),

	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_AES),

	HWCAP_CAP(SYS_ID_ISAR5_EL1, ID_ISAR5_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_COMPAT_HWCAP2, COMPAT_HWCAP2_SHA1),

arch/arm64/kernel/cpuinfo.c

+2 −0
Original line number Diff line number Diff line
@@ -146,6 +146,8 @@ static const char *const compat_hwcap_str[] = { 
	[COMPAT_KERNEL_HWCAP(VFPD32)]	= NULL,	/* Not possible on arm64 */

	[COMPAT_KERNEL_HWCAP(LPAE)]	= "lpae",

	[COMPAT_KERNEL_HWCAP(EVTSTRM)]	= "evtstrm",

	[COMPAT_KERNEL_HWCAP(FPHP)]	= "fphp",

	[COMPAT_KERNEL_HWCAP(ASIMDHP)]	= "asimdhp",

};



#define COMPAT_KERNEL_HWCAP2(x)	const_ilog2(COMPAT_HWCAP2_ ## x)