Commit 84508131 authored by Serge Semin's avatar Serge Semin Committed by Krzysztof Kozlowski
Browse files

dt-bindings: memory: synopsys,ddrc-ecc: Detach Zynq DDRC controller support 



The Zynq A05 DDRC controller has nothing in common with DW uMCTL2 DDRC:
the CSRs layout is absolutely different and it doesn't support IRQs unlike
DW uMCTL2 DDR controller of all versions (v1.x, v2.x and v3.x). Thus there
is no any reason to have these controllers described in the same bindings.
Let's split the DT-schema up.

Note since the synopsys,ddrc-ecc.yaml schema describes the Synopsys DW
uMCTL2 DDR controller only, we need to accordingly fix the device
descriptions.

Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220910194237.10142-15-Sergey.Semin@baikalelectronics.ru
parent 9f8fb803

Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml

+20 −43
Original line number Diff line number Diff line
@@ -4,7 +4,7 @@ 
$id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Synopsys IntelliDDR Multi Protocol memory controller

title: Synopsys DesignWare Universal Multi-Protocol Memory Controller



maintainers:

  - Krzysztof Kozlowski <krzk@kernel.org>
@@ -12,21 +12,22 @@ maintainers: 
  - Michal Simek <michal.simek@xilinx.com>



description: |

  The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and

  32-bit bus width configurations.

  Synopsys DesignWare Enhanced uMCTL2 DDR Memory Controller is capable of

  working with the memory devices supporting up to (LP)DDR4 protocol. It can

  be equipped with SEC/DEC ECC feature if DRAM data bus width is either

  16-bits or 32-bits or 64-bits wide.



  The Zynq DDR ECC controller has an optional ECC support in half-bus width

  (16-bit) configuration.



  These both ECC controllers correct single bit ECC errors and detect double bit

  ECC errors.

  For instance the ZynqMP DDR controller is based on the DW uMCTL2 v2.40a

  controller. It has an optional SEC/DEC ECC support in 64- and 32-bits

  bus width configurations.



properties:

  compatible:

    enum:

      - snps,ddrc-3.80a

      - xlnx,zynq-ddrc-a05

      - xlnx,zynqmp-ddrc-2.40a

    oneOf:

      - description: Synopsys DW uMCTL2 DDR controller v3.80a

        const: snps,ddrc-3.80a

      - description: Xilinx ZynqMP DDR controller v2.40a

        const: xlnx,zynqmp-ddrc-2.40a



  interrupts:

    maxItems: 1
@@ -37,40 +38,16 @@ properties: 
required:

  - compatible

  - reg



allOf:

  - if:

      properties:

        compatible:

          contains:

            enum:

              - snps,ddrc-3.80a

              - xlnx,zynqmp-ddrc-2.40a

    then:

      required:

  - interrupts

    else:

      properties:

        interrupts: false



additionalProperties: false



examples:

  - |

    memory-controller@f8006000 {

        compatible = "xlnx,zynq-ddrc-a05";

        reg = <0xf8006000 0x1000>;

    };



  - |

    axi {

        #address-cells = <2>;

        #size-cells = <2>;



    memory-controller@fd070000 {

      compatible = "xlnx,zynqmp-ddrc-2.40a";

            reg = <0x0 0xfd070000 0x0 0x30000>;

      reg = <0xfd070000 0x30000>;

      interrupt-parent = <&gic>;

      interrupts = <0 112 4>;

    };

    };
 
...

Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml

0 → 100644
+38 −0
Original line number Diff line number Diff line 
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause

%YAML 1.2

---

$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynq-ddrc-a05.yaml#

$schema: http://devicetree.org/meta-schemas/core.yaml#



title: Zynq A05 DDR Memory Controller



maintainers:

  - Krzysztof Kozlowski <krzk@kernel.org>

  - Manish Narani <manish.narani@xilinx.com>

  - Michal Simek <michal.simek@xilinx.com>



description:

  The Zynq DDR ECC controller has an optional ECC support in half-bus width

  (16-bit) configuration. It is cappable of correcting single bit ECC errors

  and detecting double bit ECC errors.



properties:

  compatible:

    const: xlnx,zynq-ddrc-a05



  reg:

    maxItems: 1



required:

  - compatible

  - reg



additionalProperties: false



examples:

  - |

    memory-controller@f8006000 {

      compatible = "xlnx,zynq-ddrc-a05";

      reg = <0xf8006000 0x1000>;

    };

...

MAINTAINERS

+1 −0
Original line number Diff line number Diff line
@@ -3087,6 +3087,7 @@ W: http://wiki.xilinx.com 
T:	git https://github.com/Xilinx/linux-xlnx.git

F:	Documentation/devicetree/bindings/i2c/cdns,i2c-r1p10.yaml

F:	Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml

F:	Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml

F:	Documentation/devicetree/bindings/spi/xlnx,zynq-qspi.yaml

F:	arch/arm/mach-zynq/

F:	drivers/clocksource/timer-cadence-ttc.c