Commit 843af59e authored by Peng Fan's avatar Peng Fan Committed by Shawn Guo
Browse files

arm64: dts: imx8mp-venice-gw74xx: correct pad settings 



According to RM bit layout, BIT3 and BIT0 are reserved.
  8  7   6   5   4   3  2 1  0
 PE HYS PUE ODE FSEL X  DSE  X

Should not set reserved bit.

Fixes: 7899eb6c ("arm64: dts: imx: Add i.MX8M Plus Gateworks gw7400 dts support")
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Reviewed-by: default avatarRasmus Villemoes <rasmus.villemoes@prevas.dk>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 0836de51

arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts

+58 −58
Original line number Diff line number Diff line
@@ -622,15 +622,15 @@ 


	pinctrl_hog: hoggrp {

		fsl,pins = <

			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09	0x40000041 /* DIO0 */

			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x40000041 /* DIO1 */

			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x40000041 /* M2SKT_OFF# */

			MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17	0x40000159 /* PCIE1_WDIS# */

			MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18	0x40000159 /* PCIE2_WDIS# */

			MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14	0x40000159 /* PCIE3_WDIS# */

			MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06	0x40000041 /* M2SKT_RST# */

			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x40000159 /* M2SKT_WDIS# */

			MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00	0x40000159 /* M2SKT_GDIS# */

			MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09	0x40000040 /* DIO0 */

			MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11	0x40000040 /* DIO1 */

			MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14	0x40000040 /* M2SKT_OFF# */

			MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17	0x40000150 /* PCIE1_WDIS# */

			MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18	0x40000150 /* PCIE2_WDIS# */

			MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14	0x40000150 /* PCIE3_WDIS# */

			MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06	0x40000040 /* M2SKT_RST# */

			MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18	0x40000150 /* M2SKT_WDIS# */

			MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00	0x40000150 /* M2SKT_GDIS# */

			MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01	0x40000104 /* UART_TERM */

			MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31	0x40000104 /* UART_RS485 */

			MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00	0x40000104 /* UART_HALF */
@@ -639,47 +639,47 @@ 


	pinctrl_accel: accelgrp {

		fsl,pins = <

			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07	0x159

			MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07	0x150

		>;

	};



	pinctrl_eqos: eqosgrp {

		fsl,pins = <

			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x3

			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x3

			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x91

			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x91

			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x91

			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x91

			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x91

			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x91

			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x1f

			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x1f

			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x1f

			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x1f

			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x1f

			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x1f

			MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30		0x141 /* RST# */

			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x159 /* IRQ# */

			MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC				0x2

			MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO				0x2

			MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0		0x90

			MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1		0x90

			MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2		0x90

			MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3		0x90

			MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	0x90

			MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL		0x90

			MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0		0x16

			MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1		0x16

			MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2		0x16

			MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3		0x16

			MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL		0x16

			MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	0x16

			MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30		0x140 /* RST# */

			MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28		0x150 /* IRQ# */

		>;

	};



	pinctrl_fec: fecgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x91

			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x91

			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x91

			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x91

			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x91

			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x91

			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x1f

			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x1f

			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x1f

			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x1f

			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x1f

			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x1f

			MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN	0x141

			MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT	0x141

			MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0		0x90

			MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1		0x90

			MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2		0x90

			MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3		0x90

			MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC		0x90

			MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL	0x90

			MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0		0x16

			MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1		0x16

			MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2		0x16

			MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3		0x16

			MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL	0x16

			MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC		0x16

			MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN	0x140

			MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT	0x140

		>;

	};
@@ -692,61 +692,61 @@ 


	pinctrl_gsc: gscgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x159

			MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20	0x150

		>;

	};



	pinctrl_i2c1: i2c1grp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c3

			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c3

			MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL		0x400001c2

			MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA		0x400001c2

		>;

	};



	pinctrl_i2c2: i2c2grp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c3

			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c3

			MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL		0x400001c2

			MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA		0x400001c2

		>;

	};



	pinctrl_i2c3: i2c3grp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c3

			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c3

			MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL		0x400001c2

			MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA		0x400001c2

		>;

	};



	pinctrl_i2c4: i2c4grp {

		fsl,pins = <

			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c3

			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c3

			MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL		0x400001c2

			MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA		0x400001c2

		>;

	};



	pinctrl_ksz: kszgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x159 /* IRQ# */

			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02	0x141 /* RST# */

			MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29	0x150 /* IRQ# */

			MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02	0x140 /* RST# */

		>;

	};



	pinctrl_gpio_leds: ledgrp {

		fsl,pins = <

			MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15	0x19

			MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16	0x19

			MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15	0x10

			MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16	0x10

		>;

	};



	pinctrl_pmic: pmicgrp {

		fsl,pins = <

			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07	0x141

			MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07	0x140

		>;

	};



	pinctrl_pps: ppsgrp {

		fsl,pins = <

			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x141

			MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12	0x140

		>;

	};
@@ -758,13 +758,13 @@ 


	pinctrl_reg_usb2: regusb2grp {

		fsl,pins = <

			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06	0x141

			MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06	0x140

		>;

	};



	pinctrl_reg_wifi: regwifigrp {

		fsl,pins = <

			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x119

			MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09	0x110

		>;

	};
@@ -811,7 +811,7 @@ 


	pinctrl_uart3_gpio: uart3gpiogrp {

		fsl,pins = <

			MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08	0x119

			MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08	0x110

		>;

	};