Commit 84368d88 authored by Linus Torvalds's avatar Linus Torvalds
Browse files
Pull ARM SoC fixes from Arnd Bergmann:
 "Another set of devicetree and code changes for SoC platforms, notably:

   - DT schema warning fixes for i.MX

   - Functional fixes for i.MX tqma8mqml-mba8mx USB and i.MX8M OCOTP

   - MAINTAINERS updates for Hisilicon and RISC-V, documenting which
     RISC-V SoC specific patches will now get merged through the SoC
     tree in the future.

   - A code fix for at91 suspend, to work around broken hardware

   - A devicetree fix for lan966x/pcb8291 LED support

   - Lots of DT fixes for Qualcomm SoCs, mostly fixing minor problems
     like incorrect register sizes and schema warnings. One fix makes
     the UFS controller work on sc8280xp, and six fixes address the same
     regulator problem in a variety of platforms"

* tag 'soc-fixes-6.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (31 commits)
  MAINTAINERS: repair Microchip corei2c driver entry
  MAINTAINERS: add an entry for StarFive devicetrees
  MAINTAINERS: generify the Microchip RISC-V entry name
  MAINTAINERS: add entries for misc. RISC-V SoC drivers and devicetrees
  MAINTAINERS: git://github.com -> https://github.com for HiSilicon
  soc: imx8m: Enable OCOTP clock before reading the register
  arm64: dts: imx93-pinfunc: drop execution permission
  arm64: dts: imx8mn: Fix NAND controller size-cells
  arm64: dts: imx8mm: Fix NAND controller size-cells
  ARM: dts: imx7: Fix NAND controller size-cells
  arm64: dts: imx8mm-tqma8mqml-mba8mx: Fix USB DR
  ARM: at91: pm: avoid soft resetting AC DLL
  ARM: dts: lan966x: Enable sgpio on pcb8291
  arm64: dts: qcom: sm8250: Disable the not yet supported cluster idle state
  ARM: dts: at91: sama7g5: fix signal name of pin PB2
  arm64: dts: qcom: sc7280: Add the reset reg for lpass audiocc on SC7280
  arm64: dts: qcom: sc8280xp: fix UFS PHY serdes size
  arm64: dts: qcom: sc8280xp: drop broken DP PHY nodes
  arm64: dts: qcom: sc8280xp: fix USB PHY PCS registers
  arm64: dts: qcom: sc8280xp: fix USB1 PHY RX1 registers
  ...
parents ae753340 0d6a10dc
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+31 −5
Original line number Diff line number Diff line
@@ -2197,7 +2197,7 @@ M: Wei Xu <xuwei5@hisilicon.com>
L:	linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S:	Supported
W:	http://www.hisilicon.com
T:	git git://github.com/hisilicon/linux-hisi.git
T:	git https://github.com/hisilicon/linux-hisi.git
F:	arch/arm/boot/dts/hi3*
F:	arch/arm/boot/dts/hip*
F:	arch/arm/boot/dts/hisi*
@@ -13625,6 +13625,12 @@ S: Supported
F:	drivers/misc/atmel-ssc.c
F:	include/linux/atmel-ssc.h
MICROCHIP SOC DRIVERS
M:	Conor Dooley <conor@kernel.org>
S:	Supported
T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
F:	drivers/soc/microchip/
MICROCHIP USB251XB DRIVER
M:	Richard Leitner <richard.leitner@skidata.com>
L:	linux-usb@vger.kernel.org
@@ -17723,7 +17729,7 @@ F: arch/riscv/
N:	riscv
K:	riscv
RISC-V/MICROCHIP POLARFIRE SOC SUPPORT
RISC-V MICROCHIP FPGA SUPPORT
M:	Conor Dooley <conor.dooley@microchip.com>
M:	Daire McNamara <daire.mcnamara@microchip.com>
L:	linux-riscv@lists.infradead.org
@@ -17741,17 +17747,26 @@ F: Documentation/devicetree/bindings/usb/microchip,mpfs-musb.yaml
F:	arch/riscv/boot/dts/microchip/
F:	drivers/char/hw_random/mpfs-rng.c
F:	drivers/clk/microchip/clk-mpfs.c
F:	drivers/i2c/busses/i2c-microchip-core.c
F:	drivers/i2c/busses/i2c-microchip-corei2c.c
F:	drivers/mailbox/mailbox-mpfs.c
F:	drivers/pci/controller/pcie-microchip-host.c
F:	drivers/reset/reset-mpfs.c
F:	drivers/rtc/rtc-mpfs.c
F:	drivers/soc/microchip/
F:	drivers/soc/microchip/mpfs-sys-controller.c
F:	drivers/spi/spi-microchip-core-qspi.c
F:	drivers/spi/spi-microchip-core.c
F:	drivers/usb/musb/mpfs.c
F:	include/soc/microchip/mpfs.h
RISC-V MISC SOC SUPPORT
M:	Conor Dooley <conor@kernel.org>
L:	linux-riscv@lists.infradead.org
S:	Maintained
Q:	https://patchwork.kernel.org/project/linux-riscv/list/
T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
F:	Documentation/devicetree/bindings/riscv/
F:	arch/riscv/boot/dts/
RNBD BLOCK DRIVERS
M:	Md. Haris Iqbal <haris.iqbal@ionos.com>
M:	Jack Wang <jinpu.wang@ionos.com>
@@ -18778,7 +18793,6 @@ M: Palmer Dabbelt <palmer@dabbelt.com>
M:	Paul Walmsley <paul.walmsley@sifive.com>
L:	linux-riscv@lists.infradead.org
S:	Supported
T:	git https://github.com/sifive/riscv-linux.git
N:	sifive
K:	[^@]sifive
@@ -18797,6 +18811,13 @@ S: Maintained
F:	Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml
F:	drivers/dma/sf-pdma/
SIFIVE SOC DRIVERS
M:	Conor Dooley <conor@kernel.org>
L:	linux-riscv@lists.infradead.org
S:	Maintained
T:	git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
F:	drivers/soc/sifive/
SILEAD TOUCHSCREEN DRIVER
M:	Hans de Goede <hdegoede@redhat.com>
L:	linux-input@vger.kernel.org
@@ -19598,6 +19619,11 @@ M: Ion Badulescu <ionut@badula.org>
S:	Odd Fixes
F:	drivers/net/ethernet/adaptec/starfire*
STARFIVE DEVICETREES
M:	Emil Renner Berthing <kernel@esmil.dk>
S:	Maintained
F:	arch/riscv/boot/dts/starfive/
STARFIVE JH7100 CLOCK DRIVERS
M:	Emil Renner Berthing <kernel@esmil.dk>
S:	Maintained
+2 −2
Original line number Diff line number Diff line
@@ -1273,7 +1273,7 @@
		gpmi: nand-controller@33002000 {
			compatible = "fsl,imx7d-gpmi-nand";
			#address-cells = <1>;
			#size-cells = <1>;
			#size-cells = <0>;
			reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
			reg-names = "gpmi-nand", "bch";
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
+20 −0
Original line number Diff line number Diff line
@@ -69,6 +69,12 @@
		pins = "GPIO_35", "GPIO_36";
		function = "can0_b";
	};

	sgpio_a_pins: sgpio-a-pins {
		/* SCK, D0, D1, LD */
		pins = "GPIO_32", "GPIO_33", "GPIO_34", "GPIO_35";
		function = "sgpio_a";
	};
};

&can0 {
@@ -118,6 +124,20 @@
	status = "okay";
};

&sgpio {
	pinctrl-0 = <&sgpio_a_pins>;
	pinctrl-names = "default";
	microchip,sgpio-port-ranges = <0 3>, <8 11>;
	status = "okay";

	gpio@0 {
		ngpios = <64>;
	};
	gpio@1 {
		ngpios = <64>;
	};
};

&switch {
	status = "okay";
};
+1 −1
Original line number Diff line number Diff line
@@ -261,7 +261,7 @@
#define PIN_PB2__FLEXCOM6_IO0		PINMUX_PIN(PIN_PB2, 2, 1)
#define PIN_PB2__ADTRG			PINMUX_PIN(PIN_PB2, 3, 1)
#define PIN_PB2__A20			PINMUX_PIN(PIN_PB2, 4, 1)
#define PIN_PB2__FLEXCOM11_IO0		PINMUX_PIN(PIN_PB2, 6, 3)
#define PIN_PB2__FLEXCOM11_IO1		PINMUX_PIN(PIN_PB2, 6, 3)
#define PIN_PB3				35
#define PIN_PB3__GPIO			PINMUX_PIN(PIN_PB3, 0, 0)
#define PIN_PB3__RF1			PINMUX_PIN(PIN_PB3, 1, 1)
+6 −1
Original line number Diff line number Diff line
@@ -169,10 +169,15 @@ sr_ena_2:
	cmp	tmp1, #UDDRC_STAT_SELFREF_TYPE_SW
	bne	sr_ena_2

	/* Put DDR PHY's DLL in bypass mode for non-backup modes. */
	/* Disable DX DLLs for non-backup modes. */
	cmp	r7, #AT91_PM_BACKUP
	beq	sr_ena_3

	/* Do not soft reset the AC DLL. */
	ldr	tmp1, [r3, DDR3PHY_ACDLLCR]
	bic	tmp1, tmp1, DDR3PHY_ACDLLCR_DLLSRST
	str	tmp1, [r3, DDR3PHY_ACDLLCR]

	/* Disable DX DLLs. */
	ldr	tmp1, [r3, #DDR3PHY_DX0DLLCR]
	orr	tmp1, tmp1, #DDR3PHY_DXDLLCR_DLLDIS
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