Commit 840d10b6 authored by Bjorn Andersson's avatar Bjorn Andersson Committed by Rob Clark
Browse files

drm: msm: Add 680 gpu to the adreno gpu list 



This patch adds a Adreno 680 entry to the gpulist.

Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210725032002.3961691-1-bjorn.andersson@linaro.org


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 192f4ee3

drivers/gpu/drm/msm/adreno/a6xx_gmu.c

+3 −2
Original line number Diff line number Diff line
@@ -521,7 +521,8 @@ static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu) 


	if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu))

		pdc_in_aop = true;

	else if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu))

	else if (adreno_is_a618(adreno_gpu) || adreno_is_a640(adreno_gpu) ||

		 adreno_is_a680(adreno_gpu))

		pdc_address_offset = 0x30090;

	else

		pdc_address_offset = 0x30080;
@@ -1526,7 +1527,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) 
			SZ_16M - SZ_16K, 0x04000);

		if (ret)

			goto err_memory;

	} else if (adreno_is_a640(adreno_gpu)) {

	} else if (adreno_is_a640(adreno_gpu) || adreno_is_a680(adreno_gpu)) {

		ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,

			SZ_256K - SZ_16K, 0x04000);

		if (ret)

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+10 −5
Original line number Diff line number Diff line
@@ -683,7 +683,7 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 
	if (adreno_is_a618(adreno_gpu))

		return;



	if (adreno_is_a640(adreno_gpu))

	if (adreno_is_a640(adreno_gpu) || adreno_is_a680(adreno_gpu))

		amsbc = 1;



	if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) {
@@ -764,7 +764,7 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, 
	 * a660 targets have all the critical security fixes from the start

	 */

	if (adreno_is_a618(adreno_gpu) || adreno_is_a630(adreno_gpu) ||

		adreno_is_a640(adreno_gpu)) {

	    adreno_is_a640(adreno_gpu) || adreno_is_a680(adreno_gpu)) {

		/*

		 * If the lowest nibble is 0xa that is an indication that this

		 * microcode has been patched. The actual version is in dword
@@ -904,7 +904,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu) 
	a6xx_set_hwcg(gpu, true);



	/* VBIF/GBIF start*/

	if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) {

	if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu) ||

	    adreno_is_a680(adreno_gpu)) {

		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE0, 0x00071620);

		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE1, 0x00071620);

		gpu_write(gpu, REG_A6XX_GBIF_QSB_SIDE2, 0x00071620);
@@ -942,7 +943,8 @@ static int a6xx_hw_init(struct msm_gpu *gpu) 
	gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804);

	gpu_write(gpu, REG_A6XX_UCHE_CACHE_WAYS, 0x4);



	if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu))

	if (adreno_is_a640(adreno_gpu) || adreno_is_a650_family(adreno_gpu) ||

	    adreno_is_a680(adreno_gpu))

		gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);

	else

		gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x010000c0);
@@ -957,7 +959,10 @@ static int a6xx_hw_init(struct msm_gpu *gpu) 
	/* Setting the primFifo thresholds default values,

	 * and vccCacheSkipDis=1 bit (0x200) for A640 and newer

	*/

	if (adreno_is_a640(adreno_gpu) || adreno_is_7c3(adreno_gpu))

	if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);

	else if (adreno_is_a640(adreno_gpu) || adreno_is_a680(adreno_gpu) ||

			adreno_is_7c3(adreno_gpu))

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00200200);

	else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu))

		gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200);

drivers/gpu/drm/msm/adreno/a6xx_hfi.c

+1 −1
Original line number Diff line number Diff line
@@ -458,7 +458,7 @@ static int a6xx_hfi_send_bw_table(struct a6xx_gmu *gmu) 


	if (adreno_is_a618(adreno_gpu))

		a618_build_bw_table(&msg);

	else if (adreno_is_a640(adreno_gpu))

	else if (adreno_is_a640(adreno_gpu) || adreno_is_a680(adreno_gpu))

		a640_build_bw_table(&msg);

	else if (adreno_is_a650(adreno_gpu))

		a650_build_bw_table(&msg);

drivers/gpu/drm/msm/adreno/adreno_device.c

+13 −0
Original line number Diff line number Diff line
@@ -309,6 +309,19 @@ static const struct adreno_info gpulist[] = { 
		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init = a6xx_gpu_init,

		.hwcg = a660_hwcg,

	}, {

		.rev = ADRENO_REV(6, 8, 0, ANY_ID),

		.revn = 680,

		.name = "A680",

		.fw = {

			[ADRENO_FW_SQE] = "a630_sqe.fw",

			[ADRENO_FW_GMU] = "a640_gmu.bin",

		},

		.gmem = SZ_2M,

		.inactive_period = DRM_MSM_INACTIVE_PERIOD,

		.init = a6xx_gpu_init,

		.zapfw = "a640_zap.mdt",

		.hwcg = a640_hwcg,

	},

};

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+5 −0
Original line number Diff line number Diff line
@@ -274,6 +274,11 @@ static inline int adreno_is_a650_family(struct adreno_gpu *gpu) 
	       adreno_is_a660_family(gpu);

}



static inline int adreno_is_a680(struct adreno_gpu *gpu)

{

       return gpu->revn == 680;

}



int adreno_get_param(struct msm_gpu *gpu, uint32_t param, uint64_t *value);

const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,

		const char *fwname);