Commit 83b975b5 authored by Aidan MacDonald's avatar Aidan MacDonald Committed by Stephen Boyd
Browse files

clk: ingenic: Make PLL clock "od" field optional 



Add support for defining PLL clocks with od_bits = 0, meaning that
OD is fixed to 1 and there is no OD field in the register. In this
case od_max must also be 0, which is enforced with BUG_ON().

Signed-off-by: default avatarAidan MacDonald <aidanmacdonald.0x0@gmail.com>
Link: https://lore.kernel.org/r/20221026194345.243007-2-aidanmacdonald.0x0@gmail.com


Reviewed-by: default avatarPaul Cercueil <paul@crapouillou.net>
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 9abf2313

drivers/clk/ingenic/cgu.c

+17 −8
Original line number Diff line number Diff line
@@ -83,7 +83,7 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
	const struct ingenic_cgu_clk_info *clk_info = to_clk_info(ingenic_clk);

	struct ingenic_cgu *cgu = ingenic_clk->cgu;

	const struct ingenic_cgu_pll_info *pll_info;

	unsigned m, n, od_enc, od;

	unsigned m, n, od, od_enc = 0;

	bool bypass;

	u32 ctl;
@@ -96,8 +96,11 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
	m += pll_info->m_offset;

	n = (ctl >> pll_info->n_shift) & GENMASK(pll_info->n_bits - 1, 0);

	n += pll_info->n_offset;



	if (pll_info->od_bits > 0) {

		od_enc = ctl >> pll_info->od_shift;

		od_enc &= GENMASK(pll_info->od_bits - 1, 0);

	}



	if (pll_info->bypass_bit >= 0) {

		ctl = readl(cgu->base + pll_info->bypass_reg);
@@ -108,10 +111,14 @@ ingenic_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
			return parent_rate;

	}



	for (od = 0; od < pll_info->od_max; od++) {

	for (od = 0; od < pll_info->od_max; od++)

		if (pll_info->od_encoding[od] == od_enc)

			break;

	}



	/* if od_max = 0, od_bits should be 0 and od is fixed to 1. */

	if (pll_info->od_max == 0)

		BUG_ON(pll_info->od_bits != 0);

	else

		BUG_ON(od == pll_info->od_max);

	od++;
@@ -215,8 +222,10 @@ ingenic_pll_set_rate(struct clk_hw *hw, unsigned long req_rate, 
	ctl &= ~(GENMASK(pll_info->n_bits - 1, 0) << pll_info->n_shift);

	ctl |= (n - pll_info->n_offset) << pll_info->n_shift;



	if (pll_info->od_bits > 0) {

		ctl &= ~(GENMASK(pll_info->od_bits - 1, 0) << pll_info->od_shift);

		ctl |= pll_info->od_encoding[od - 1] << pll_info->od_shift;

	}



	writel(ctl, cgu->base + pll_info->reg);

drivers/clk/ingenic/cgu.h

+2 −1
Original line number Diff line number Diff line
@@ -33,7 +33,8 @@ 
 * @od_shift: the number of bits to shift the post-VCO divider value by (ie.

 *            the index of the lowest bit of the post-VCO divider value in

 *            the PLL's control register)

 * @od_bits: the size of the post-VCO divider field in bits

 * @od_bits: the size of the post-VCO divider field in bits, or 0 if no

 *	     OD field exists (then the OD is fixed to 1)

 * @od_max: the maximum post-VCO divider value

 * @od_encoding: a pointer to an array mapping post-VCO divider values to

 *               their encoded values in the PLL control register, or -1 for