Unverified Commit 838714f6 authored by openeuler-ci-bot's avatar openeuler-ci-bot Committed by Gitee
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!2261 backport kunpeng hccs driver and enable compiling config 

Merge Pull Request from: @huangdengdui 
 
backport the following patches:
886bdf9c soc: hisilicon: Support HCCS driver on Kunpeng SoC
47f7a255 soc: hisilicon: add sysfs entry to query information of HCCS
b51022b4 doc: soc: hisilicon: Add Kunpeng HCCS driver documentation
37696fa7 soc: kunpeng_hccs: fix size_t format string
a90d34af soc: kunpeng_hccs: add MAILBOX dependency
7d661283 soc: kunpeng_hccs: fix some sparse warnings about incorrect type
in addition, add openEuler compilation options config. 
 
Link:https://gitee.com/openeuler/kernel/pulls/2261

 

Reviewed-by: default avatarFred Kimmy <xweikong@163.com>
Reviewed-by: default avatarLiu Chao <liuchao173@huawei.com>
Signed-off-by: default avatarJialin Zhang <zhangjialin11@huawei.com>
parents 0dc80a61 02e8df6d

Documentation/ABI/testing/sysfs-devices-platform-kunpeng_hccs

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What:		/sys/devices/platform/HISI04Bx:00/chipX/all_linked

What:		/sys/devices/platform/HISI04Bx:00/chipX/linked_full_lane

What:		/sys/devices/platform/HISI04Bx:00/chipX/crc_err_cnt

Date:		November 2023

KernelVersion:	6.6

Contact:	Huisong Li <lihuisong@huawei.org>

Description:

		The /sys/devices/platform/HISI04Bx:00/chipX/ directory

		contains read-only attributes exposing some summarization

		information of all HCCS ports under a specified chip.

		The X in 'chipX' indicates the Xth chip on platform.



		There are following attributes in this directory:



		================= ==== =========================================

		all_linked:       (RO) if all enabled ports on this chip are

				       linked (bool).

		linked_full_lane: (RO) if all linked ports on this chip are full

				       lane (bool).

		crc_err_cnt:      (RO) total CRC err count for all ports on this

				       chip.

		================= ==== =========================================



What:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/all_linked

What:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/linked_full_lane

What:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/crc_err_cnt

Date:		November 2023

KernelVersion:	6.6

Contact:	Huisong Li <lihuisong@huawei.org>

Description:

		The /sys/devices/platform/HISI04Bx:00/chipX/dieY/ directory

		contains read-only attributes exposing some summarization

		information of all HCCS ports under a specified die.

		The Y in 'dieY' indicates the hardware id of the die on chip who

		has chip id X.



		There are following attributes in this directory:



		================= ==== =========================================

		all_linked:       (RO) if all enabled ports on this die are

				       linked (bool).

		linked_full_lane: (RO) if all linked ports on this die are full

				       lane (bool).

		crc_err_cnt:      (RO) total CRC err count for all ports on this

				       die.

		================= ==== =========================================



What:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/type

What:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mode

What:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/enable

What:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/cur_lane_num

What:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/link_fsm

What:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/lane_mask

What:		/sys/devices/platform/HISI04Bx:00/chipX/dieY/hccsN/crc_err_cnt

Date:		November 2023

KernelVersion:	6.6

Contact:	Huisong Li <lihuisong@huawei.org>

Description:

		The /sys/devices/platform/HISI04Bx/chipX/dieX/hccsN/ directory

		contains read-only attributes exposing information about

		a HCCS port. The N value in 'hccsN' indicates this port id.

		The X in 'chipX' indicates the ID of the chip to which the

		HCCS port belongs. For example, X ranges from to 'n - 1' if the

		chip number on platform is n.

		The Y in 'dieY' indicates the hardware id of the die to which

		the hccs port belongs.

		Note: type, lane_mode and enable are fixed attributes on running

		platform.



		The HCCS port have the following attributes:



		============= ==== =============================================

		type:         (RO) port type (string), e.g. HCCS-v1 -> H32

		lane_mode:    (RO) the lane mode of this port (string), e.g. x8

		enable:       (RO) indicate if this port is enabled (bool).

		cur_lane_num: (RO) current lane number of this port.

		link_fsm:     (RO) link finite state machine of this port.

		lane_mask:    (RO) current lane mask of this port, every bit

			           indicates a lane.

		crc_err_cnt:  (RO) CRC err count on this port.

		============= ==== =============================================

MAINTAINERS

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@@ -7945,6 +7945,13 @@ S: Maintained 
W:	https://www.hisilicon.com

F:	drivers/i2c/busses/i2c-hisi.c









HISILICON KUNPENG SOC HCCS DRIVER









M:	Huisong Li <lihuisong@huawei.com>









S:	Maintained









F:	Documentation/ABI/testing/sysfs-devices-platform-kunpeng_hccs









F:	drivers/soc/hisilicon/kunpeng_hccs.c









F:	drivers/soc/hisilicon/kunpeng_hccs.h

















HISILICON LPC BUS DRIVER









M:	john.garry@huawei.com









S:	Maintained
































arch/arm64/configs/openeuler_defconfig



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@@ -6020,6 +6020,14 @@ CONFIG_QCOM_KRYO_L2_ACCESSORS=y







#









# CONFIG_XILINX_VCU is not set









# end of Xilinx SoC drivers



















#









# Hisilicon SoC drivers









#









CONFIG_KUNPENG_HCCS=m









# CONFIG_HISI_HBMDEV is not set









# CONFIG_HISI_HBMCACHE is not set









# end of Hisilicon SoC drivers









# end of SOC (System On Chip) specific Drivers



















# CONFIG_PM_DEVFREQ is not set
































drivers/soc/hisilicon/Kconfig



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−5






























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# SPDX-License-Identifier: GPL-2.0









#









# Hisilicon SoC drivers









#









menu "Hisilicon SoC driver support"









# SPDX-License-Identifier: GPL-2.0-only



















menu "Hisilicon SoC drivers"









	depends on ARCH_HISI || COMPILE_TEST



















config KUNPENG_HCCS









	tristate "HCCS driver on Kunpeng SoC"









	depends on ACPI









	depends on MAILBOX









	depends on ARM64 || COMPILE_TEST









	help









	  The Huawei Cache Coherence System (HCCS) is a multi-chip









	  interconnection bus protocol.









	  The performance of application may be affected if some HCCS









	  ports are not in full lane status, have a large number of CRC









	  errors and so on.



















	  Say M here if you want to include support for querying the









	  health status and port information of HCCS on Kunpeng SoC.



















config HISI_HBMDEV









	tristate "add extra support for hbm memory device"
































drivers/soc/hisilicon/Makefile



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−1






























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# SPDX-License-Identifier: GPL-2.0









# SPDX-License-Identifier: GPL-2.0-only









obj-$(CONFIG_KUNPENG_HCCS)	+= kunpeng_hccs.o



















obj-$(CONFIG_HISI_HBMDEV)	+= hisi_hbmdev.o









obj-$(CONFIG_HISI_HBMCACHE)	+= hisi_hbmcache.o