Commit 835dc5ac authored by Krzysztof Kozlowski's avatar Krzysztof Kozlowski
Browse files

clk: samsung: exynos5250: do not define number of clocks in bindings 



Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore these numbers of
clocks should not be in the bindings, as that prevents changing them.

Define number of clocks per each clock controller inside the driver
directly.

Reviewed-by: default avatarAlim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: default avatarChanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20230808082738.122804-4-krzysztof.kozlowski@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 826951d9

drivers/clk/samsung/clk-exynos5250.c

+4 −1
Original line number Diff line number Diff line
@@ -100,6 +100,9 @@ 
#define PWR_CTRL2_CORE2_UP_RATIO		(1 << 4)

#define PWR_CTRL2_CORE1_UP_RATIO		(1 << 0)



/* NOTE: Must be equal to the last clock ID increased by one */

#define CLKS_NR					(CLK_MOUT_VPLLSRC + 1)



/* list of PLLs to be registered */

enum exynos5250_plls {

	apll, mpll, cpll, epll, vpll, gpll, bpll,
@@ -797,7 +800,7 @@ static void __init exynos5250_clk_init(struct device_node *np) 
		panic("%s: unable to determine soc\n", __func__);

	}



	ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);

	ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);

	hws = ctx->clk_data.hws;



	samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,