Commit 83228ebb authored by Fangzhi Zuo's avatar Fangzhi Zuo Committed by Alex Deucher
Browse files

drm/amd/display: Add DP 2.0 HPO Stream Encoder 



HW Blocks:

        +--------+  +-----+  +------+
        |  OPTC  |  | HDA |  | HUBP |
        +--------+  +-----+  +------+
            |          |        |
            |          |        |
    HPO ====|==========|========|====
     |      |          v        |
     |      |       +-----+     |
     |      |       | APG |     |
     |      |       +-----+     |
     |      |          |        |
     v      v          v        v
           +----------------------+
           |  HPO Stream Encoder  |
           +----------------------+

[squash in warning fixes - Alex]

Signed-off-by: default avatarFangzhi Zuo <Jerry.Zuo@amd.com>
Reviewed-by: default avatarNicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 61452908

drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c

+33 −0
Original line number Diff line number Diff line
@@ -466,6 +466,39 @@ void dcn10_log_hw_state(struct dc *dc, 


	log_mpc_crc(dc, log_ctx);



	{

		int hpo_dp_link_enc_count = 0;



		if (pool->hpo_dp_stream_enc_count > 0) {

			DTN_INFO("DP HPO S_ENC:  Enabled  OTG   Format   Depth   Vid   SDP   Compressed  Link\n");

			for (i = 0; i < pool->hpo_dp_stream_enc_count; i++) {

				struct hpo_dp_stream_encoder_state hpo_dp_se_state = {0};

				struct hpo_dp_stream_encoder *hpo_dp_stream_enc = pool->hpo_dp_stream_enc[i];



				if (hpo_dp_stream_enc && hpo_dp_stream_enc->funcs->read_state) {

					hpo_dp_stream_enc->funcs->read_state(hpo_dp_stream_enc, &hpo_dp_se_state);



					DTN_INFO("[%d]:                 %d    %d   %6s       %d     %d     %d            %d     %d\n",

							hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0,

							hpo_dp_se_state.stream_enc_enabled,

							hpo_dp_se_state.otg_inst,

							(hpo_dp_se_state.pixel_encoding == 0) ? "4:4:4" :

									((hpo_dp_se_state.pixel_encoding == 1) ? "4:2:2" :

									(hpo_dp_se_state.pixel_encoding == 2) ? "4:2:0" : "Y-Only"),

							(hpo_dp_se_state.component_depth == 0) ? 6 :

									((hpo_dp_se_state.component_depth == 1) ? 8 :

									(hpo_dp_se_state.component_depth == 2) ? 10 : 12),

							hpo_dp_se_state.vid_stream_enabled,

							hpo_dp_se_state.sdp_enabled,

							hpo_dp_se_state.compressed_format,

							hpo_dp_se_state.mapped_to_link_enc);

				}

			}



			DTN_INFO("\n");

		}

	}



	DTN_INFO_END();

}

drivers/gpu/drm/amd/display/dc/dcn31/Makefile

+1 −1
Original line number Diff line number Diff line
@@ -12,7 +12,7 @@ 


DCN31 = dcn31_resource.o dcn31_hubbub.o dcn31_hwseq.o dcn31_init.o dcn31_hubp.o \

	dcn31_dccg.o dcn31_optc.o dcn31_dio_link_encoder.o dcn31_panel_cntl.o \

	dcn31_apg.o

	dcn31_apg.o dcn31_hpo_dp_stream_encoder.o



ifdef CONFIG_X86

CFLAGS_$(AMDDALPATH)/dc/dcn31/dcn31_resource.o := -msse

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.c

0 → 100644
+747 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hpo_dp_stream_encoder.h

0 → 100644
+241 −0
Original line number Diff line number Diff line 
/*

 * Copyright 2019 Advanced Micro Devices, Inc.

 *

 * Permission is hereby granted, free of charge, to any person obtaining a

 * copy of this software and associated documentation files (the "Software"),

 * to deal in the Software without restriction, including without limitation

 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

 * and/or sell copies of the Software, and to permit persons to whom the

 * Software is furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL

 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR

 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,

 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR

 * OTHER DEALINGS IN THE SOFTWARE.

 *

 * Authors: AMD

 *

 */



#ifndef __DAL_DCN31_HPO_DP_STREAM_ENCODER_H__

#define __DAL_DCN31_HPO_DP_STREAM_ENCODER_H__



#include "dcn30/dcn30_vpg.h"

#include "dcn31/dcn31_apg.h"

#include "stream_encoder.h"





#define DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(hpo_dp_stream_encoder)\

	container_of(hpo_dp_stream_encoder, struct dcn31_hpo_dp_stream_encoder, base)





/* Define MSA_DATA_LANE_[0-3] fields to make programming easier */

#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_0__SHIFT   0x0

#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_1__SHIFT   0x8

#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_2__SHIFT   0x10

#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_3__SHIFT   0x18

#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_0_MASK     0x000000FFL

#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_1_MASK     0x0000FF00L

#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_2_MASK     0x00FF0000L

#define DP_SYM32_ENC_VID_MSA__MSA_DATA_LANE_3_MASK     0xFF000000L





#define DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id) \

	SR(DP_STREAM_MAPPER_CONTROL0),\

	SR(DP_STREAM_MAPPER_CONTROL1),\

	SR(DP_STREAM_MAPPER_CONTROL2),\

	SR(DP_STREAM_MAPPER_CONTROL3),\

	SRI(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id),\

	SRI(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id),\

	SRI(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id),\

	SRI(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id),\

	SRI(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_MSA3, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_MSA4, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_MSA5, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_MSA6, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_MSA7, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_MSA8, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_MSA_CONTROL, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_FIFO_CONTROL, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_STREAM_CONTROL, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_VBID_CONTROL, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_SDP_CONTROL, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_SDP_GSP_CONTROL0, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_SDP_GSP_CONTROL2, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_SDP_GSP_CONTROL3, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_SDP_GSP_CONTROL5, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_SDP_GSP_CONTROL11, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_SDP_AUDIO_CONTROL0, DP_SYM32_ENC, id),\

	SRI(DP_SYM32_ENC_VID_CRC_CONTROL, DP_SYM32_ENC, id)



#define DCN3_1_HPO_DP_STREAM_ENC_REGS \

	uint32_t DP_STREAM_MAPPER_CONTROL0;\

	uint32_t DP_STREAM_MAPPER_CONTROL1;\

	uint32_t DP_STREAM_MAPPER_CONTROL2;\

	uint32_t DP_STREAM_MAPPER_CONTROL3;\

	uint32_t DP_STREAM_ENC_CLOCK_CONTROL;\

	uint32_t DP_STREAM_ENC_INPUT_MUX_CONTROL;\

	uint32_t DP_STREAM_ENC_AUDIO_CONTROL;\

	uint32_t DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0;\

	uint32_t DP_SYM32_ENC_CONTROL;\

	uint32_t DP_SYM32_ENC_VID_PIXEL_FORMAT;\

	uint32_t DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL;\

	uint32_t DP_SYM32_ENC_VID_MSA0;\

	uint32_t DP_SYM32_ENC_VID_MSA1;\

	uint32_t DP_SYM32_ENC_VID_MSA2;\

	uint32_t DP_SYM32_ENC_VID_MSA3;\

	uint32_t DP_SYM32_ENC_VID_MSA4;\

	uint32_t DP_SYM32_ENC_VID_MSA5;\

	uint32_t DP_SYM32_ENC_VID_MSA6;\

	uint32_t DP_SYM32_ENC_VID_MSA7;\

	uint32_t DP_SYM32_ENC_VID_MSA8;\

	uint32_t DP_SYM32_ENC_VID_MSA_CONTROL;\

	uint32_t DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL;\

	uint32_t DP_SYM32_ENC_VID_FIFO_CONTROL;\

	uint32_t DP_SYM32_ENC_VID_STREAM_CONTROL;\

	uint32_t DP_SYM32_ENC_VID_VBID_CONTROL;\

	uint32_t DP_SYM32_ENC_SDP_CONTROL;\

	uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL0;\

	uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL2;\

	uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL3;\

	uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL5;\

	uint32_t DP_SYM32_ENC_SDP_GSP_CONTROL11;\

	uint32_t DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL;\

	uint32_t DP_SYM32_ENC_SDP_AUDIO_CONTROL0;\

	uint32_t DP_SYM32_ENC_VID_CRC_CONTROL





#define DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(mask_sh)\

	SE_SF(DP_STREAM_MAPPER_CONTROL0, DP_STREAM_LINK_TARGET, mask_sh),\

	SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC_CLOCK_EN, mask_sh),\

	SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL, mask_sh),\

	SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL, mask_sh),\

	SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_RESET, mask_sh),\

	SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_RESET_DONE, mask_sh),\

	SE_SF(DP_STREAM_ENC0_DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, FIFO_ENABLE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL, DP_SYM32_ENC_RESET, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL, DP_SYM32_ENC_RESET_DONE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_CONTROL, DP_SYM32_ENC_ENABLE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT, PIXEL_ENCODING_TYPE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT, UNCOMPRESSED_PIXEL_ENCODING, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT, UNCOMPRESSED_COMPONENT_DEPTH, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_MSA_DOUBLE_BUFFER_CONTROL, MSA_DOUBLE_BUFFER_ENABLE, mask_sh),\

	SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_0, mask_sh),\

	SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_1, mask_sh),\

	SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_2, mask_sh),\

	SE_SF(DP_SYM32_ENC_VID_MSA, MSA_DATA_LANE_3, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL, PIXEL_TO_SYMBOL_FIFO_RESET, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL, PIXEL_TO_SYMBOL_FIFO_RESET_DONE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_FIFO_CONTROL, PIXEL_TO_SYMBOL_FIFO_ENABLE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL, VID_STREAM_ENABLE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_STREAM_CONTROL, VID_STREAM_STATUS, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL, VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_VBID_CONTROL, VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_CONTROL, SDP_STREAM_ENABLE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_PAYLOAD_SIZE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL0, GSP_TRANSMISSION_LINE_NUMBER, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_TRANSMISSION_LINE_NUMBER, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_GSP_CONTROL5, GSP_SOF_REFERENCE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_METADATA_PACKET_CONTROL, METADATA_PACKET_ENABLE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, AUDIO_MUTE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ASP_ENABLE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ATP_ENABLE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, AIP_ENABLE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_SDP_AUDIO_CONTROL0, ACM_ENABLE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, CRC_ENABLE, mask_sh),\

	SE_SF(DP_SYM32_ENC0_DP_SYM32_ENC_VID_CRC_CONTROL, CRC_CONT_MODE_ENABLE, mask_sh)





#define DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(type) \

	type DP_STREAM_LINK_TARGET;\

	type DP_STREAM_ENC_CLOCK_EN;\

	type DP_STREAM_ENC_INPUT_MUX_PIXEL_STREAM_SOURCE_SEL;\

	type DP_STREAM_ENC_INPUT_MUX_AUDIO_STREAM_SOURCE_SEL;\

	type FIFO_RESET;\

	type FIFO_RESET_DONE;\

	type FIFO_ENABLE;\

	type DP_SYM32_ENC_RESET;\

	type DP_SYM32_ENC_RESET_DONE;\

	type DP_SYM32_ENC_ENABLE;\

	type PIXEL_ENCODING_TYPE;\

	type UNCOMPRESSED_PIXEL_ENCODING;\

	type UNCOMPRESSED_COMPONENT_DEPTH;\

	type PIXEL_FORMAT_DOUBLE_BUFFER_ENABLE;\

	type MSA_DOUBLE_BUFFER_ENABLE;\

	type MSA_DATA_LANE_0;\

	type MSA_DATA_LANE_1;\

	type MSA_DATA_LANE_2;\

	type MSA_DATA_LANE_3;\

	type PIXEL_TO_SYMBOL_FIFO_RESET;\

	type PIXEL_TO_SYMBOL_FIFO_RESET_DONE;\

	type PIXEL_TO_SYMBOL_FIFO_ENABLE;\

	type VID_STREAM_ENABLE;\

	type VID_STREAM_STATUS;\

	type VBID_6_COMPRESSEDSTREAM_FLAG_SOF_REFERENCE;\

	type VBID_6_COMPRESSEDSTREAM_FLAG_LINE_NUMBER;\

	type SDP_STREAM_ENABLE;\

	type AUDIO_MUTE;\

	type ASP_ENABLE;\

	type ATP_ENABLE;\

	type AIP_ENABLE;\

	type ACM_ENABLE;\

	type GSP_VIDEO_CONTINUOUS_TRANSMISSION_ENABLE;\

	type GSP_PAYLOAD_SIZE;\

	type GSP_TRANSMISSION_LINE_NUMBER;\

	type GSP_SOF_REFERENCE;\

	type METADATA_PACKET_ENABLE;\

	type CRC_ENABLE;\

	type CRC_CONT_MODE_ENABLE





struct dcn31_hpo_dp_stream_encoder_registers {

	DCN3_1_HPO_DP_STREAM_ENC_REGS;

};



struct dcn31_hpo_dp_stream_encoder_shift {

	DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint8_t);

};



struct dcn31_hpo_dp_stream_encoder_mask {

	DCN3_1_HPO_DP_STREAM_ENC_REG_FIELD_LIST(uint32_t);

};



struct dcn31_hpo_dp_stream_encoder {

	struct hpo_dp_stream_encoder base;

	const struct dcn31_hpo_dp_stream_encoder_registers *regs;

	const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift;

	const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask;

};





void dcn31_hpo_dp_stream_encoder_construct(

	struct dcn31_hpo_dp_stream_encoder *enc3,

	struct dc_context *ctx,

	struct dc_bios *bp,

	uint32_t inst,

	enum engine_id eng_id,

	struct vpg *vpg,

	struct apg *apg,

	const struct dcn31_hpo_dp_stream_encoder_registers *regs,

	const struct dcn31_hpo_dp_stream_encoder_shift *hpo_se_shift,

	const struct dcn31_hpo_dp_stream_encoder_mask *hpo_se_mask);





#endif   // __DAL_DCN31_HPO_STREAM_ENCODER_H__

drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c

+85 −0
Original line number Diff line number Diff line
@@ -52,6 +52,7 @@ 
#include "dcn30/dcn30_vpg.h"

#include "dcn30/dcn30_afmt.h"

#include "dcn30/dcn30_dio_stream_encoder.h"

#include "dcn31/dcn31_hpo_dp_stream_encoder.h"

#include "dcn31/dcn31_apg.h"

#include "dcn31/dcn31_dio_link_encoder.h"

#include "dce/dce_clock_source.h"
@@ -564,6 +565,26 @@ static const struct dcn10_link_enc_mask le_mask = { 
	DPP_REG_LIST_DCN30(id),\

}



#define hpo_dp_stream_encoder_reg_list(id)\

[id] = {\

	DCN3_1_HPO_DP_STREAM_ENC_REG_LIST(id)\

}



static const struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[] = {

	hpo_dp_stream_encoder_reg_list(0),

	hpo_dp_stream_encoder_reg_list(1),

	hpo_dp_stream_encoder_reg_list(2),

	hpo_dp_stream_encoder_reg_list(3),

};



static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {

	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)

};



static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {

	DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)

};



static const struct dcn3_dpp_registers dpp_regs[] = {

	dpp_regs(0),

	dpp_regs(1),
@@ -900,6 +921,7 @@ static const struct resource_caps res_cap_dcn31 = { 
	.num_audio = 5,

	.num_stream_encoder = 5,

	.num_dig_link_enc = 5,

	.num_hpo_dp_stream_encoder = 4,

	.num_pll = 5,

	.num_dwb = 1,

	.num_ddc = 5,
@@ -1330,6 +1352,52 @@ static struct stream_encoder *dcn31_stream_encoder_create( 
	return &enc1->base;

}



static struct hpo_dp_stream_encoder *dcn31_hpo_dp_stream_encoder_create(

	enum engine_id eng_id,

	struct dc_context *ctx)

{

	struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;

	struct vpg *vpg;

	struct apg *apg;

	uint32_t hpo_dp_inst;

	uint32_t vpg_inst;

	uint32_t apg_inst;



	ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));

	hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;



	/* Mapping of VPG register blocks to HPO DP block instance:

	 * VPG[6] -> HPO_DP[0]

	 * VPG[7] -> HPO_DP[1]

	 * VPG[8] -> HPO_DP[2]

	 * VPG[9] -> HPO_DP[3]

	 */

	vpg_inst = hpo_dp_inst + 6;



	/* Mapping of APG register blocks to HPO DP block instance:

	 * APG[0] -> HPO_DP[0]

	 * APG[1] -> HPO_DP[1]

	 * APG[2] -> HPO_DP[2]

	 * APG[3] -> HPO_DP[3]

	 */

	apg_inst = hpo_dp_inst;



	/* allocate HPO stream encoder and create VPG sub-block */

	hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);

	vpg = dcn31_vpg_create(ctx, vpg_inst);

	apg = dcn31_apg_create(ctx, apg_inst);



	if (!hpo_dp_enc31 || !vpg || !apg)

		return NULL;



	dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,

					hpo_dp_inst, eng_id, vpg, apg,

					&hpo_dp_stream_enc_regs[hpo_dp_inst],

					&hpo_dp_se_shift, &hpo_dp_se_mask);



	return &hpo_dp_enc31->base;

}



static struct dce_hwseq *dcn31_hwseq_create(

	struct dc_context *ctx)

{
@@ -1347,6 +1415,7 @@ static const struct resource_create_funcs res_create_funcs = { 
	.read_dce_straps = read_dce_straps,

	.create_audio = dcn31_create_audio,

	.create_stream_encoder = dcn31_stream_encoder_create,

	.create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,

	.create_hwseq = dcn31_hwseq_create,

};
@@ -1354,6 +1423,7 @@ static const struct resource_create_funcs res_create_maximus_funcs = { 
	.read_dce_straps = NULL,

	.create_audio = NULL,

	.create_stream_encoder = NULL,

	.create_hpo_dp_stream_encoder = dcn31_hpo_dp_stream_encoder_create,

	.create_hwseq = dcn31_hwseq_create,

};
@@ -1376,6 +1446,21 @@ static void dcn31_resource_destruct(struct dcn31_resource_pool *pool) 
		}

	}



	for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {

		if (pool->base.hpo_dp_stream_enc[i] != NULL) {

			if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {

				kfree(DCN30_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));

				pool->base.hpo_dp_stream_enc[i]->vpg = NULL;

			}

			if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {

				kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));

				pool->base.hpo_dp_stream_enc[i]->apg = NULL;

			}

			kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));

			pool->base.hpo_dp_stream_enc[i] = NULL;

		}

	}



	for (i = 0; i < pool->base.res_cap->num_dsc; i++) {

		if (pool->base.dscs[i] != NULL)

			dcn20_dsc_destroy(&pool->base.dscs[i]);