Commit 82d89369 authored by Huang Rui's avatar Huang Rui Committed by Rafael J. Wysocki
Browse files

x86/ACPI: CPPC: Move AMD maximum frequency ratio setting function into x86 CPPC



The AMD maximum frequency ratio setting function depends on CPPC, so the
x86 CPPC implementation file is better space for this function.

Signed-off-by: default avatarHuang Rui <ray.huang@amd.com>
[ rjw: Subject adjustment ]
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent fd8af343
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+9 −0
Original line number Diff line number Diff line
@@ -226,4 +226,13 @@ void init_freq_invariance_cppc(void);
#define init_freq_invariance_cppc init_freq_invariance_cppc
#endif

#ifdef CONFIG_ACPI_CPPC_LIB
bool amd_set_max_freq_ratio(u64 *ratio);
#else
static inline bool amd_set_max_freq_ratio(u64 *ratio)
{
	return false;
}
#endif

#endif /* _ASM_X86_TOPOLOGY_H */
+40 −0
Original line number Diff line number Diff line
@@ -6,6 +6,8 @@

#include <acpi/cppc_acpi.h>
#include <asm/msr.h>
#include <asm/processor.h>
#include <asm/topology.h>

/* Refer to drivers/acpi/cppc_acpi.c for the description of functions */

@@ -47,3 +49,41 @@ int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val)
	}
	return err;
}

bool amd_set_max_freq_ratio(u64 *ratio)
{
	struct cppc_perf_caps perf_caps;
	u64 highest_perf, nominal_perf;
	u64 perf_ratio;
	int rc;

	if (!ratio)
		return false;

	rc = cppc_get_perf_caps(0, &perf_caps);
	if (rc) {
		pr_debug("Could not retrieve perf counters (%d)\n", rc);
		return false;
	}

	highest_perf = amd_get_highest_perf();
	nominal_perf = perf_caps.nominal_perf;

	if (!highest_perf || !nominal_perf) {
		pr_debug("Could not retrieve highest or nominal performance\n");
		return false;
	}

	perf_ratio = div_u64(highest_perf * SCHED_CAPACITY_SCALE, nominal_perf);
	/* midpoint between max_boost and max_P */
	perf_ratio = (perf_ratio + SCHED_CAPACITY_SCALE) >> 1;
	if (!perf_ratio) {
		pr_debug("Non-zero highest/nominal perf values led to a 0 ratio\n");
		return false;
	}

	*ratio = perf_ratio;
	arch_set_max_freq_ratio(false);

	return true;
}
+1 −43
Original line number Diff line number Diff line
@@ -2097,48 +2097,6 @@ static bool intel_set_max_freq_ratio(void)
	return true;
}

#ifdef CONFIG_ACPI_CPPC_LIB
static bool amd_set_max_freq_ratio(void)
{
	struct cppc_perf_caps perf_caps;
	u64 highest_perf, nominal_perf;
	u64 perf_ratio;
	int rc;

	rc = cppc_get_perf_caps(0, &perf_caps);
	if (rc) {
		pr_debug("Could not retrieve perf counters (%d)\n", rc);
		return false;
	}

	highest_perf = amd_get_highest_perf();
	nominal_perf = perf_caps.nominal_perf;

	if (!highest_perf || !nominal_perf) {
		pr_debug("Could not retrieve highest or nominal performance\n");
		return false;
	}

	perf_ratio = div_u64(highest_perf * SCHED_CAPACITY_SCALE, nominal_perf);
	/* midpoint between max_boost and max_P */
	perf_ratio = (perf_ratio + SCHED_CAPACITY_SCALE) >> 1;
	if (!perf_ratio) {
		pr_debug("Non-zero highest/nominal perf values led to a 0 ratio\n");
		return false;
	}

	arch_turbo_freq_ratio = perf_ratio;
	arch_set_max_freq_ratio(false);

	return true;
}
#else
static bool amd_set_max_freq_ratio(void)
{
	return false;
}
#endif

static void init_counter_refs(void)
{
	u64 aperf, mperf;
@@ -2187,7 +2145,7 @@ static void init_freq_invariance(bool secondary, bool cppc_ready)
		if (!cppc_ready) {
			return;
		}
		ret = amd_set_max_freq_ratio();
		ret = amd_set_max_freq_ratio(&arch_turbo_freq_ratio);
	}

	if (ret) {