Commit 829e1611 authored by Kunkun Jiang's avatar Kunkun Jiang Committed by Zheng Zengkai
Browse files

iommu/arm-smmu-v3: Add feature detection for BBML 

virt inclusion
category: feature
bugzilla: https://gitee.com/openeuler/kernel/issues/I3ZUKK


CVE: NA

------------------------------

This detects BBML feature and if SMMU supports it, transfer BBMLx
quirk to io-pgtable.

Co-developed-by: default avatarKeqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: default avatarKunkun Jiang <jiangkunkun@huawei.com>
Reviewed-by: default avatarKeqian Zhu <zhukeqian1@huawei.com>
Signed-off-by: default avatarZheng Zengkai <zhengzengkai@huawei.com>
parent c2f77dfa

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c

+19 −0
Original line number Diff line number Diff line
@@ -2343,6 +2343,11 @@ static int arm_smmu_domain_finalise(struct iommu_domain *domain, 
	if (smmu->features & ARM_SMMU_FEAT_HD)

		pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_ARM_HD;



	if (smmu->features & ARM_SMMU_FEAT_BBML1)

		pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_ARM_BBML1;

	else if (smmu->features & ARM_SMMU_FEAT_BBML2)

		pgtbl_cfg.quirks |= IO_PGTABLE_QUIRK_ARM_BBML2;



	pgtbl_ops = alloc_io_pgtable_ops(fmt, &pgtbl_cfg, smmu_domain);

	if (!pgtbl_ops)

		return -ENOMEM;
@@ -4023,6 +4028,20 @@ static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) 


	/* IDR3 */

	reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3);

	switch (FIELD_GET(IDR3_BBML, reg)) {

	case IDR3_BBML0:

		break;

	case IDR3_BBML1:

		smmu->features |= ARM_SMMU_FEAT_BBML1;

		break;

	case IDR3_BBML2:

		smmu->features |= ARM_SMMU_FEAT_BBML2;

		break;

	default:

		dev_err(smmu->dev, "unknown/unsupported BBM behavior level\n");

		return -ENXIO;

	}



	if (FIELD_GET(IDR3_RIL, reg))

		smmu->features |= ARM_SMMU_FEAT_RANGE_INV;

drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h

+6 −0
Original line number Diff line number Diff line
@@ -55,6 +55,10 @@ 
#define IDR1_SIDSIZE			GENMASK(5, 0)



#define ARM_SMMU_IDR3			0xc

#define IDR3_BBML			GENMASK(12, 11)

#define IDR3_BBML0			0

#define IDR3_BBML1			1

#define IDR3_BBML2			2

#define IDR3_RIL			(1 << 10)



#define ARM_SMMU_IDR5			0x14
@@ -651,6 +655,8 @@ struct arm_smmu_device { 
#define ARM_SMMU_FEAT_E2H		(1 << 18)

#define ARM_SMMU_FEAT_HA		(1 << 19)

#define ARM_SMMU_FEAT_HD		(1 << 20)

#define ARM_SMMU_FEAT_BBML1		(1 << 21)

#define ARM_SMMU_FEAT_BBML2		(1 << 22)

	u32				features;



#define ARM_SMMU_OPT_SKIP_PREFETCH	(1 << 0)