Commit 8296ff0a authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Rob Clark
Browse files

drm/msm/a6xx: Add support for A619_holi 



A619_holi is a GMU-less variant of the already-supported A619 GPU.
It's present on at least SM4350 (holi) and SM6375 (blair). No mesa
changes are required. Add the required kernel-side support for it.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/542775/


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent 9bad3760

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+25 −2
Original line number Diff line number Diff line
@@ -911,6 +911,9 @@ static void a6xx_set_ubwc_config(struct msm_gpu *gpu) 
	if (adreno_is_a618(adreno_gpu))

		return;



	if (adreno_is_a619_holi(adreno_gpu))

		hbb_lo = 0;



	if (adreno_is_a640_family(adreno_gpu))

		amsbc = 1;
@@ -1135,7 +1138,12 @@ static int hw_init(struct msm_gpu *gpu) 
	}



	/* Clear GBIF halt in case GX domain was not collapsed */

	if (a6xx_has_gbif(adreno_gpu)) {

	if (adreno_is_a619_holi(adreno_gpu)) {

		gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);

		gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, 0);

		/* Let's make extra sure that the GPU can access the memory.. */

		mb();

	} else if (a6xx_has_gbif(adreno_gpu)) {

		gpu_write(gpu, REG_A6XX_GBIF_HALT, 0);

		gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 0);

		/* Let's make extra sure that the GPU can access the memory.. */
@@ -1144,6 +1152,9 @@ static int hw_init(struct msm_gpu *gpu) 


	gpu_write(gpu, REG_A6XX_RBBM_SECVID_TSB_CNTL, 0);



	if (adreno_is_a619_holi(adreno_gpu))

		a6xx_sptprac_enable(gmu);



	/*

	 * Disable the trusted memory range - we don't actually supported secure

	 * memory rendering at this point in time and we don't want to block off
@@ -1760,12 +1771,18 @@ static void a6xx_llc_slices_init(struct platform_device *pdev, 
#define GBIF_CLIENT_HALT_MASK		BIT(0)

#define GBIF_ARB_HALT_MASK		BIT(1)

#define VBIF_XIN_HALT_CTRL0_MASK	GENMASK(3, 0)

#define VBIF_RESET_ACK_MASK		0xF0

#define GPR0_GBIF_HALT_REQUEST		0x1E0



void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu, bool gx_off)

{

	struct msm_gpu *gpu = &adreno_gpu->base;



	if (!a6xx_has_gbif(adreno_gpu)) {

	if (adreno_is_a619_holi(adreno_gpu)) {

		gpu_write(gpu, REG_A6XX_RBBM_GPR0_CNTL, GPR0_GBIF_HALT_REQUEST);

		spin_until((gpu_read(gpu, REG_A6XX_RBBM_VBIF_GX_RESET_STATUS) &

				(VBIF_RESET_ACK_MASK)) == VBIF_RESET_ACK_MASK);

	} else if (!a6xx_has_gbif(adreno_gpu)) {

		gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, VBIF_XIN_HALT_CTRL0_MASK);

		spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &

				(VBIF_XIN_HALT_CTRL0_MASK)) == VBIF_XIN_HALT_CTRL0_MASK);
@@ -1861,6 +1878,9 @@ static int a6xx_pm_resume(struct msm_gpu *gpu) 
	if (ret)

		goto err_bulk_clk;



	if (adreno_is_a619_holi(adreno_gpu))

		a6xx_sptprac_enable(gmu);



	/* If anything goes south, tear the GPU down piece by piece.. */

	if (ret) {

err_bulk_clk:
@@ -1920,6 +1940,9 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu) 
	/* Drain the outstanding traffic on memory buses */

	a6xx_bus_clear_pending_transactions(adreno_gpu, true);



	if (adreno_is_a619_holi(adreno_gpu))

		a6xx_sptprac_disable(gmu);



	clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);



	pm_runtime_put_sync(gmu->gxpd);

drivers/gpu/drm/msm/adreno/adreno_gpu.h

+5 −0
Original line number Diff line number Diff line
@@ -263,6 +263,11 @@ static inline int adreno_is_a619(const struct adreno_gpu *gpu) 
	return adreno_is_revn(gpu, 619);

}



static inline int adreno_is_a619_holi(const struct adreno_gpu *gpu)

{

	return adreno_is_a619(gpu) && adreno_has_gmu_wrapper(gpu);

}



static inline int adreno_is_a630(const struct adreno_gpu *gpu)

{

	return adreno_is_revn(gpu, 630);