Commit 82929a21 authored by Matt Roper's avatar Matt Roper
Browse files

drm/i915: Correct SFC_DONE register offset 



The register offset for SFC_DONE was missing a '0' at the end, causing
us to read from a non-existent register address.  We only use this
register in error state dumps so the mistake hasn't caused any real
problems, but fixing it will hopefully make the error state dumps a bit
more useful for debugging.

Fixes: e50dbdbf ("drm/i915/tgl: Add SFC instdone to error state")
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: default avatarMatt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210728233411.2365788-1-matthew.d.roper@intel.com


Reviewed-by: default avatarMika Kuoppala <mika.kuoppala@linux.intel.com>
parent 615a7724

drivers/gpu/drm/i915/i915_reg.h

+1 −1
Original line number Diff line number Diff line
@@ -422,7 +422,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) 
#define   GEN12_HCP_SFC_LOCK_ACK_BIT		REG_BIT(1)

#define   GEN12_HCP_SFC_USAGE_BIT			REG_BIT(0)



#define GEN12_SFC_DONE(n)		_MMIO(0x1cc00 + (n) * 0x100)

#define GEN12_SFC_DONE(n)		_MMIO(0x1cc000 + (n) * 0x1000)

#define GEN12_SFC_DONE_MAX		4



#define RING_PP_DIR_BASE(base)		_MMIO((base) + 0x228)