Commit 8282fe00 authored by Phil Edworthy's avatar Phil Edworthy Committed by Geert Uytterhoeven
Browse files

clk: renesas: rzg2l: Add read only versions of the clk macros 



This just makes the clk tables easier to read.

Signed-off-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-7-phil.edworthy@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent ceb3bfab

drivers/clk/renesas/r9a07g043-cpg.c

+1 −2
Original line number Diff line number Diff line
@@ -98,8 +98,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = { 
	DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),

	DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),

	DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),

	DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,

		sel_pll3_3, 0, CLK_MUX_READ_ONLY),

	DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),

	DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,

		DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),

	DEF_FIXED(".pll5", CLK_PLL5, CLK_EXTAL, 125, 1),

drivers/clk/renesas/r9a07g044-cpg.c

+2 −4
Original line number Diff line number Diff line
@@ -138,15 +138,13 @@ static const struct { 
		DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),

		DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),

		DEF_FIXED(".pll3_div2_4_2", CLK_PLL3_DIV2_4_2, CLK_PLL3_DIV2_4, 1, 2),

		DEF_MUX(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3,

			sel_pll3_3, 0, CLK_MUX_READ_ONLY),

		DEF_MUX_RO(".sel_pll3_3", CLK_SEL_PLL3_3, SEL_PLL3_3, sel_pll3_3),

		DEF_DIV("divpl3c", CLK_DIV_PLL3_C, CLK_SEL_PLL3_3,

			DIVPL3C, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),



		DEF_FIXED(".pll5_250", CLK_PLL5_250, CLK_PLL5_FOUT3, 1, 2),

		DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),

		DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2,

			sel_gpu2, 0, CLK_MUX_READ_ONLY),

		DEF_MUX_RO(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2, sel_gpu2),

		DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL),

		DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2),

		DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4, sel_pll5_4),

drivers/clk/renesas/rzg2l-cpg.h

+9 −0
Original line number Diff line number Diff line
@@ -138,11 +138,20 @@ enum clk_types { 
#define DEF_DIV(_name, _id, _parent, _conf, _dtable, _flag) \

	DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \

		 .parent = _parent, .dtable = _dtable, .flag = _flag)

#define DEF_DIV_RO(_name, _id, _parent, _conf, _dtable) \

	DEF_TYPE(_name, _id, CLK_TYPE_DIV, .conf = _conf, \

		 .parent = _parent, .dtable = _dtable, \

		 .flag = CLK_DIVIDER_READ_ONLY)

#define DEF_MUX(_name, _id, _conf, _parent_names, _flag, _mux_flags) \

	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \

		 .parent_names = _parent_names, \

		 .num_parents = ARRAY_SIZE(_parent_names), \

		 .flag = _flag, .mux_flags = _mux_flags)

#define DEF_MUX_RO(_name, _id, _conf, _parent_names) \

	DEF_TYPE(_name, _id, CLK_TYPE_MUX, .conf = _conf, \

		 .parent_names = _parent_names, \

		 .num_parents = ARRAY_SIZE(_parent_names), \

		 .mux_flags = CLK_MUX_READ_ONLY)

#define DEF_SD_MUX(_name, _id, _conf, _parent_names) \

	DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \

		 .parent_names = _parent_names, \