Commit 822b84ec authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Add missing WA and MCLK validation 



When the commit fff7eb56 ("drm/amd/display: Don't set dram clock
change requirement for SubVP") was merged, we missed some parts
associated with the MCLK switch. This commit adds all the missing parts.

Fixes: fff7eb56 ("drm/amd/display: Don't set dram clock change requirement for SubVP")
Reviewed-by: default avatarAurabindo Pillai <aurabindo.pillai@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent ce560ac4

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_hwseq.c

+1 −0
Original line number Diff line number Diff line
@@ -948,6 +948,7 @@ void dcn32_init_hw(struct dc *dc) 
	if (dc->ctx->dmub_srv) {

		dc_dmub_srv_query_caps_cmd(dc->ctx->dmub_srv->dmub);

		dc->caps.dmub_caps.psr = dc->ctx->dmub_srv->dmub->feature_caps.psr;

		dc->caps.dmub_caps.mclk_sw = dc->ctx->dmub_srv->dmub->feature_caps.fw_assisted_mclk_switch;

	}

}

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

+1 −1
Original line number Diff line number Diff line
@@ -2023,7 +2023,7 @@ int dcn32_populate_dml_pipes_from_context( 
	// In general cases we want to keep the dram clock change requirement

	// (prefer configs that support MCLK switch). Only override to false

	// for SubVP

	if (subvp_in_use)

	if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || subvp_in_use)

		context->bw_ctx.dml.soc.dram_clock_change_requirement_final = false;

	else

		context->bw_ctx.dml.soc.dram_clock_change_requirement_final = true;

drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c

+17 −1
Original line number Diff line number Diff line
@@ -368,6 +368,8 @@ void dcn30_fpu_update_soc_for_wm_a(struct dc *dc, struct dc_state *context) 
	dc_assert_fp_enabled();



	if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) {

		if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching ||

				context->bw_ctx.dml.soc.dram_clock_change_latency_us == 0)

			context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us;

		context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us;

		context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us;
@@ -563,6 +565,20 @@ void dcn30_fpu_calculate_wm_and_dlg( 
		pipe_idx++;

	}



	// WA: restrict FPO to use first non-strobe mode (NV24 BW issue)

	if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching &&

			dc->dml.soc.num_chans <= 4 &&

			context->bw_ctx.dml.vba.DRAMSpeed <= 1700 &&

			context->bw_ctx.dml.vba.DRAMSpeed >= 1500) {



		for (i = 0; i < dc->dml.soc.num_states; i++) {

			if (dc->dml.soc.clock_limits[i].dram_speed_mts > 1700) {

				context->bw_ctx.dml.vba.DRAMSpeed = dc->dml.soc.clock_limits[i].dram_speed_mts;

				break;

			}

		}

	}



	dcn20_calculate_dlg_params(dc, context, pipes, pipe_cnt, vlevel);



	if (!pstate_en)