Commit 82121d15 authored by Jiansong Chen's avatar Jiansong Chen Committed by Alex Deucher
Browse files

drm/amdgpu/powerplay: add smu support for navy_flounder 



Now navy_flounder will reuse the smu11 driver_if header and ppt
functions for sienna_cichlid. Later navy_flounder can maintain
its own version if the compatibility is broken.

Signed-off-by: default avatarJiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 92278375

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

+1 −0
Original line number Original line Diff line number Diff line
@@ -602,6 +602,7 @@ static int smu_set_funcs(struct amdgpu_device *adev) 
		smu->od_enabled =false;

		smu->od_enabled =false;

		break;

		break;

	case CHIP_SIENNA_CICHLID:

	case CHIP_SIENNA_CICHLID:

	case CHIP_NAVY_FLOUNDER:

		sienna_cichlid_set_ppt_funcs(smu);

		sienna_cichlid_set_ppt_funcs(smu);

		break;

		break;

	case CHIP_RENOIR:

	case CHIP_RENOIR:

drivers/gpu/drm/amd/powerplay/inc/smu_v11_0.h

+1 −0
Original line number Original line Diff line number Diff line
@@ -31,6 +31,7 @@ 
#define SMU11_DRIVER_IF_VERSION_NV12 0x33

#define SMU11_DRIVER_IF_VERSION_NV12 0x33

#define SMU11_DRIVER_IF_VERSION_NV14 0x36

#define SMU11_DRIVER_IF_VERSION_NV14 0x36

#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33

#define SMU11_DRIVER_IF_VERSION_Sienna_Cichlid 0x33

#define SMU11_DRIVER_IF_VERSION_Navy_Flounder 0x2B





/* MP Apertures */

/* MP Apertures */

#define MP0_Public			0x03800000

#define MP0_Public			0x03800000

drivers/gpu/drm/amd/powerplay/smu_v11_0.c

+14 −1
Original line number Original line Diff line number Diff line
@@ -59,6 +59,7 @@ MODULE_FIRMWARE("amdgpu/navi10_smc.bin"); 
MODULE_FIRMWARE("amdgpu/navi14_smc.bin");

MODULE_FIRMWARE("amdgpu/navi14_smc.bin");

MODULE_FIRMWARE("amdgpu/navi12_smc.bin");

MODULE_FIRMWARE("amdgpu/navi12_smc.bin");

MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");

MODULE_FIRMWARE("amdgpu/sienna_cichlid_smc.bin");

MODULE_FIRMWARE("amdgpu/navy_flounder_smc.bin");





#define SMU11_VOLTAGE_SCALE 4

#define SMU11_VOLTAGE_SCALE 4
@@ -173,6 +174,9 @@ int smu_v11_0_init_microcode(struct smu_context *smu) 
	case CHIP_SIENNA_CICHLID:

	case CHIP_SIENNA_CICHLID:

		chip_name = "sienna_cichlid";

		chip_name = "sienna_cichlid";

		break;

		break;

	case CHIP_NAVY_FLOUNDER:

		chip_name = "navy_flounder";

		break;

	default:

	default:

		dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);

		dev_err(adev->dev, "Unsupported ASIC type %d\n", adev->asic_type);

		return -EINVAL;

		return -EINVAL;
@@ -305,6 +309,9 @@ int smu_v11_0_check_fw_version(struct smu_context *smu) 
	case CHIP_SIENNA_CICHLID:

	case CHIP_SIENNA_CICHLID:

		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;

		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Sienna_Cichlid;

		break;

		break;

	case CHIP_NAVY_FLOUNDER:

		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_Navy_Flounder;

		break;

	default:

	default:

		dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);

		dev_err(smu->adev->dev, "smu unsupported asic type:%d.\n", smu->adev->asic_type);

		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;

		smu->smc_driver_if_version = SMU11_DRIVER_IF_VERSION_INV;
@@ -386,7 +393,8 @@ int smu_v11_0_setup_pptable(struct smu_context *smu) 
	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;

	hdr = (const struct smc_firmware_header_v1_0 *) adev->pm.fw->data;

	version_major = le16_to_cpu(hdr->header.header_version_major);

	version_major = le16_to_cpu(hdr->header.header_version_major);

	version_minor = le16_to_cpu(hdr->header.header_version_minor);

	version_minor = le16_to_cpu(hdr->header.header_version_minor);

	if (version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) {

	if ((version_major == 2 && smu->smu_table.boot_values.pp_table_id > 0) ||

	    adev->asic_type == CHIP_NAVY_FLOUNDER) {

		dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);

		dev_info(adev->dev, "use driver provided pptable %d\n", smu->smu_table.boot_values.pp_table_id);

		switch (version_minor) {

		switch (version_minor) {

		case 0:

		case 0:
@@ -818,6 +826,11 @@ int smu_v11_0_set_tool_table_location(struct smu_context *smu) 
int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)

int smu_v11_0_init_display_count(struct smu_context *smu, uint32_t count)

{

{

	int ret = 0;

	int ret = 0;

	struct amdgpu_device *adev = smu->adev;



	/* Navy_Flounder do not support to change display num currently */

	if (adev->asic_type == CHIP_NAVY_FLOUNDER)

		return 0;





	if (!smu->pm_enabled)

	if (!smu->pm_enabled)

		return ret;

		return ret;