Loading drivers/mtd/nand/nand_base.c +18 −0 Original line number Diff line number Diff line Loading @@ -82,6 +82,20 @@ static struct nand_ecclayout nand_oob_64 = { .length = 38}} }; static struct nand_ecclayout nand_oob_128 = { .eccbytes = 48, .eccpos = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127}, .oobfree = { {.offset = 2, .length = 78}} }; static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state); Loading Loading @@ -2638,6 +2652,9 @@ int nand_scan_tail(struct mtd_info *mtd) case 64: chip->ecc.layout = &nand_oob_64; break; case 128: chip->ecc.layout = &nand_oob_128; break; default: printk(KERN_WARNING "No oob scheme defined for " "oobsize %d\n", mtd->oobsize); Loading Loading @@ -2767,6 +2784,7 @@ int nand_scan_tail(struct mtd_info *mtd) break; case 4: case 8: case 16: mtd->subpage_sft = 2; break; } Loading include/linux/mtd/nand.h +2 −2 Original line number Diff line number Diff line Loading @@ -43,8 +43,8 @@ extern void nand_wait_ready(struct mtd_info *mtd); * is supported now. If you add a chip with bigger oobsize/page * adjust this accordingly. */ #define NAND_MAX_OOBSIZE 64 #define NAND_MAX_PAGESIZE 2048 #define NAND_MAX_OOBSIZE 128 #define NAND_MAX_PAGESIZE 4096 /* * Constants for hardware specific CLE/ALE/NCE function Loading Loading
drivers/mtd/nand/nand_base.c +18 −0 Original line number Diff line number Diff line Loading @@ -82,6 +82,20 @@ static struct nand_ecclayout nand_oob_64 = { .length = 38}} }; static struct nand_ecclayout nand_oob_128 = { .eccbytes = 48, .eccpos = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127}, .oobfree = { {.offset = 2, .length = 78}} }; static int nand_get_device(struct nand_chip *chip, struct mtd_info *mtd, int new_state); Loading Loading @@ -2638,6 +2652,9 @@ int nand_scan_tail(struct mtd_info *mtd) case 64: chip->ecc.layout = &nand_oob_64; break; case 128: chip->ecc.layout = &nand_oob_128; break; default: printk(KERN_WARNING "No oob scheme defined for " "oobsize %d\n", mtd->oobsize); Loading Loading @@ -2767,6 +2784,7 @@ int nand_scan_tail(struct mtd_info *mtd) break; case 4: case 8: case 16: mtd->subpage_sft = 2; break; } Loading
include/linux/mtd/nand.h +2 −2 Original line number Diff line number Diff line Loading @@ -43,8 +43,8 @@ extern void nand_wait_ready(struct mtd_info *mtd); * is supported now. If you add a chip with bigger oobsize/page * adjust this accordingly. */ #define NAND_MAX_OOBSIZE 64 #define NAND_MAX_PAGESIZE 2048 #define NAND_MAX_OOBSIZE 128 #define NAND_MAX_PAGESIZE 4096 /* * Constants for hardware specific CLE/ALE/NCE function Loading