Commit 81ad4bb1 authored by Will Deacon's avatar Will Deacon
Browse files

Merge branch 'for-next/mm' into for-next/core 

Lots of cleanup to our various page-table definitions, but also some
non-critical fixes and removal of some unnecessary memory types. The
most interesting change here is the reduction of ARCH_DMA_MINALIGN back
to 64 bytes, since we're not aware of any machines that need a higher
value with the way the code is structured (only needed for non-coherent
DMA).

* for-next/mm:
  arm64: tlb: fix the TTL value of tlb_get_level
  arm64/mm: Rename ARM64_SWAPPER_USES_SECTION_MAPS
  arm64: head: fix code comments in set_cpu_boot_mode_flag
  arm64: mm: drop unused __pa(__idmap_text_start)
  arm64: mm: fix the count comments in compute_indices
  arm64/mm: Fix ttbr0 values stored in struct thread_info for software-pan
  arm64: mm: Pass original fault address to handle_mm_fault()
  arm64/mm: Drop SECTION_[SHIFT|SIZE|MASK]
  arm64/mm: Use CONT_PMD_SHIFT for ARM64_MEMSTART_SHIFT
  arm64/mm: Drop SWAPPER_INIT_MAP_SIZE
  arm64: mm: decode xFSC in mem_abort_decode()
  arm64: mm: Add is_el1_data_abort() helper
  arm64: cache: Lower ARCH_DMA_MINALIGN to 64 (L1_CACHE_BYTES)
  arm64: mm: Remove unused support for Normal-WT memory type
  arm64: acpi: Map EFI_MEMORY_WT memory as Normal-NC
  arm64: mm: Remove unused support for Device-GRE memory type
  arm64: mm: Use better bitmap_zalloc()
  arm64/mm: Make vmemmap_free() available only with CONFIG_MEMORY_HOTPLUG
  arm64/mm: Remove [PUD|PMD]_TABLE_BIT from [pud|pmd]_bad()
  arm64/mm: Validate CONFIG_PGTABLE_LEVELS
parents 078834ca 52218fcd

arch/arm64/include/asm/cache.h

+1 −1
Original line number Diff line number Diff line
@@ -47,7 +47,7 @@ 
 * cache before the transfer is done, causing old data to be seen by

 * the CPU.

 */

#define ARCH_DMA_MINALIGN	(128)

#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES



#ifdef CONFIG_KASAN_SW_TAGS

#define ARCH_SLAB_MINALIGN	(1ULL << KASAN_SHADOW_SCALE_SHIFT)

arch/arm64/include/asm/kernel-pgtable.h

+8 −11
Original line number Diff line number Diff line
@@ -18,9 +18,9 @@ 
 * 64K (section size = 512M).

 */

#ifdef CONFIG_ARM64_4K_PAGES

#define ARM64_SWAPPER_USES_SECTION_MAPS 1

#define ARM64_KERNEL_USES_PMD_MAPS 1

#else

#define ARM64_SWAPPER_USES_SECTION_MAPS 0

#define ARM64_KERNEL_USES_PMD_MAPS 0

#endif



/*
@@ -33,7 +33,7 @@ 
 * VA range, so pages required to map highest possible PA are reserved in all

 * cases.

 */

#if ARM64_SWAPPER_USES_SECTION_MAPS

#if ARM64_KERNEL_USES_PMD_MAPS

#define SWAPPER_PGTABLE_LEVELS	(CONFIG_PGTABLE_LEVELS - 1)

#define IDMAP_PGTABLE_LEVELS	(ARM64_HW_PGTABLE_LEVELS(PHYS_MASK_SHIFT) - 1)

#else
@@ -90,9 +90,9 @@ 
#define IDMAP_DIR_SIZE		(IDMAP_PGTABLE_LEVELS * PAGE_SIZE)



/* Initial memory map size */

#if ARM64_SWAPPER_USES_SECTION_MAPS

#define SWAPPER_BLOCK_SHIFT	SECTION_SHIFT

#define SWAPPER_BLOCK_SIZE	SECTION_SIZE

#if ARM64_KERNEL_USES_PMD_MAPS

#define SWAPPER_BLOCK_SHIFT	PMD_SHIFT

#define SWAPPER_BLOCK_SIZE	PMD_SIZE

#define SWAPPER_TABLE_SHIFT	PUD_SHIFT

#else

#define SWAPPER_BLOCK_SHIFT	PAGE_SHIFT
@@ -100,16 +100,13 @@ 
#define SWAPPER_TABLE_SHIFT	PMD_SHIFT

#endif



/* The size of the initial kernel direct mapping */

#define SWAPPER_INIT_MAP_SIZE	(_AC(1, UL) << SWAPPER_TABLE_SHIFT)



/*

 * Initial memory map attributes.

 */

#define SWAPPER_PTE_FLAGS	(PTE_TYPE_PAGE | PTE_AF | PTE_SHARED)

#define SWAPPER_PMD_FLAGS	(PMD_TYPE_SECT | PMD_SECT_AF | PMD_SECT_S)



#if ARM64_SWAPPER_USES_SECTION_MAPS

#if ARM64_KERNEL_USES_PMD_MAPS

#define SWAPPER_MM_MMUFLAGS	(PMD_ATTRINDX(MT_NORMAL) | SWAPPER_PMD_FLAGS)

#else

#define SWAPPER_MM_MMUFLAGS	(PTE_ATTRINDX(MT_NORMAL) | SWAPPER_PTE_FLAGS)
@@ -125,7 +122,7 @@ 
#if defined(CONFIG_ARM64_4K_PAGES)

#define ARM64_MEMSTART_SHIFT		PUD_SHIFT

#elif defined(CONFIG_ARM64_16K_PAGES)

#define ARM64_MEMSTART_SHIFT		(PMD_SHIFT + 5)

#define ARM64_MEMSTART_SHIFT		CONT_PMD_SHIFT

#else

#define ARM64_MEMSTART_SHIFT		PMD_SHIFT

#endif

arch/arm64/include/asm/memory.h

+2 −4
Original line number Diff line number Diff line
@@ -135,10 +135,8 @@ 
#define MT_NORMAL		0

#define MT_NORMAL_TAGGED	1

#define MT_NORMAL_NC		2

#define MT_NORMAL_WT		3

#define MT_DEVICE_nGnRnE	4

#define MT_DEVICE_nGnRE		5

#define MT_DEVICE_GRE		6

#define MT_DEVICE_nGnRnE	3

#define MT_DEVICE_nGnRE		4



/*

 * Memory types for Stage-2 translation

arch/arm64/include/asm/mmu_context.h

+2 −2
Original line number Diff line number Diff line
@@ -177,9 +177,9 @@ static inline void update_saved_ttbr0(struct task_struct *tsk, 
		return;



	if (mm == &init_mm)

		ttbr = __pa_symbol(reserved_pg_dir);

		ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir));

	else

		ttbr = virt_to_phys(mm->pgd) | ASID(mm) << 48;

		ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48;



	WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr);

}

arch/arm64/include/asm/pgtable-hwdef.h

+0 −7
Original line number Diff line number Diff line
@@ -71,13 +71,6 @@ 
#define PGDIR_MASK		(~(PGDIR_SIZE-1))

#define PTRS_PER_PGD		(1 << (VA_BITS - PGDIR_SHIFT))



/*

 * Section address mask and size definitions.

 */

#define SECTION_SHIFT		PMD_SHIFT

#define SECTION_SIZE		(_AC(1, UL) << SECTION_SHIFT)

#define SECTION_MASK		(~(SECTION_SIZE-1))



/*

 * Contiguous page definitions.

 */