Commit 818280d5 authored by Daniel Vetter's avatar Daniel Vetter
Browse files

Merge v5.9-rc5 into drm-next 



Paul needs 1a21e5b9 ("drm/ingenic: Fix leak of device_node
pointer") and 3b5b005e ("drm/ingenic: Fix driver not probing when
IPU port is missing") from -fixes to be able to merge further ingenic
patches into -next.

Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parents 166774a2 856deb86

.mailmap

+1 −0
Original line number Diff line number Diff line
@@ -308,6 +308,7 @@ Tony Luck <tony.luck@intel.com> 
TripleX Chung <xxx.phy@gmail.com> <triplex@zh-kernel.org>

TripleX Chung <xxx.phy@gmail.com> <zhongyu@18mail.cn>

Tsuneo Yoshioka <Tsuneo.Yoshioka@f-secure.com>

Tycho Andersen <tycho@tycho.pizza> <tycho@tycho.ws>

Uwe Kleine-König <ukleinek@informatik.uni-freiburg.de>

Uwe Kleine-König <ukl@pengutronix.de>

Uwe Kleine-König <Uwe.Kleine-Koenig@digi.com>

Documentation/admin-guide/dynamic-debug-howto.rst

+0 −1
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@@ -156,7 +156,6 @@ against. Possible keywords are::: 
  ``line-range`` cannot contain space, e.g.

  "1-30" is valid range but "1 - 30" is not.



  ``module=foo`` combined keyword=value form is interchangably accepted



The meanings of each keyword are:

Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt

+8 −8
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@@ -23,8 +23,8 @@ Required properties: 


- compatible:

    Must be one of :

    "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs

    "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI

    "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi" : MSPI+BSPI on BRCMSTB SoCs

    "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi" : Second Instance of MSPI

						   BRCMSTB  SoCs

    "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI

    			     			  			    BRCMSTB  SoCs
@@ -36,8 +36,8 @@ Required properties: 
    			     			  			    BRCMSTB  SoCs

    "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI

    			     			  			    BRCMSTB  SoCs

    "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"     : MSPI+BSPI on Cygnus, NSP

    "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"     : NS2 SoCs

    "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi"     : MSPI+BSPI on Cygnus, NSP

    "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi"     : NS2 SoCs



- reg:

    Define the bases and ranges of the associated I/O address spaces.
@@ -86,7 +86,7 @@ BRCMSTB SoC Example: 
    spi@f03e3400 {

		#address-cells = <0x1>;

		#size-cells = <0x0>;

		compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-qspi";

		compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-bcm-qspi";

		reg = <0xf03e0920 0x4 0xf03e3400 0x188 0xf03e3200 0x50>;

		reg-names = "cs_reg", "mspi", "bspi";

		interrupts = <0x6 0x5 0x4 0x3 0x2 0x1 0x0>;
@@ -149,7 +149,7 @@ BRCMSTB SoC Example: 
		#address-cells = <1>;

		#size-cells = <0>;

		clocks = <&upg_fixed>;

		compatible = "brcm,spi-brcmstb-qspi", "brcm,spi-brcmstb-mspi";

		compatible = "brcm,spi-brcmstb-mspi", "brcm,spi-bcm-qspi";

		reg = <0xf0416000 0x180>;

		reg-names = "mspi";

		interrupts = <0x14>;
@@ -160,7 +160,7 @@ BRCMSTB SoC Example: 
iProc SoC Example:



    qspi: spi@18027200 {

	compatible = "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi";

	compatible = "brcm,spi-nsp-qspi", "brcm,spi-bcm-qspi";

	reg = <0x18027200 0x184>,

	      <0x18027000 0x124>,

	      <0x1811c408 0x004>,
@@ -191,7 +191,7 @@ iProc SoC Example: 
 NS2 SoC Example:



	       qspi: spi@66470200 {

		       compatible = "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi";

		       compatible = "brcm,spi-ns2-qspi", "brcm,spi-bcm-qspi";

		       reg = <0x66470200 0x184>,

			     <0x66470000 0x124>,

			     <0x67017408 0x004>,

Documentation/driver-api/dma-buf.rst

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@@ -179,7 +179,7 @@ DMA Fence uABI/Sync File 
   :internal:



Indefinite DMA Fences

~~~~~~~~~~~~~~~~~~~~

~~~~~~~~~~~~~~~~~~~~~



At various times &dma_fence with an indefinite time until dma_fence_wait()

finishes have been proposed. Examples include:

Documentation/virt/kvm/api.rst

+18 −4
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@@ -6130,7 +6130,7 @@ HvCallSendSyntheticClusterIpi, HvCallSendSyntheticClusterIpiEx. 
8.21 KVM_CAP_HYPERV_DIRECT_TLBFLUSH

-----------------------------------



:Architecture: x86

:Architectures: x86



This capability indicates that KVM running on top of Hyper-V hypervisor

enables Direct TLB flush for its guests meaning that TLB flush
@@ -6143,19 +6143,33 @@ in CPUID and only exposes Hyper-V identification. In this case, guest 
thinks it's running on Hyper-V and only use Hyper-V hypercalls.



8.22 KVM_CAP_S390_VCPU_RESETS

-----------------------------



Architectures: s390

:Architectures: s390



This capability indicates that the KVM_S390_NORMAL_RESET and

KVM_S390_CLEAR_RESET ioctls are available.



8.23 KVM_CAP_S390_PROTECTED

---------------------------



Architecture: s390



:Architectures: s390



This capability indicates that the Ultravisor has been initialized and

KVM can therefore start protected VMs.

This capability governs the KVM_S390_PV_COMMAND ioctl and the

KVM_MP_STATE_LOAD MP_STATE. KVM_SET_MP_STATE can fail for protected

guests when the state change is invalid.



8.24 KVM_CAP_STEAL_TIME

-----------------------



:Architectures: arm64, x86



This capability indicates that KVM supports steal time accounting.

When steal time accounting is supported it may be enabled with

architecture-specific interfaces.  This capability and the architecture-

specific interfaces must be consistent, i.e. if one says the feature

is supported, than the other should as well and vice versa.  For arm64

see Documentation/virt/kvm/devices/vcpu.rst "KVM_ARM_VCPU_PVTIME_CTRL".

For x86 see Documentation/virt/kvm/msr.rst "MSR_KVM_STEAL_TIME".