Commit 813c3b53 authored by Daniel Golle's avatar Daniel Golle Committed by Stephen Boyd
Browse files

clk: mediatek: add MT7981 clock support 



Add MT7981 clock support, include topckgen, apmixedsys, infracfg and
ethernet subsystem clocks.

The drivers are based on clk-mt7981.c which can be found in MediaTek's
SDK sources. To be fit for upstream inclusion the driver has been split
into clock domains and the infracfg part has been significantly
de-bloated by removing all the 1:1 factors (aliases).

Signed-off-by: default avatarJianhui Zhao <zhaojh329@gmail.com>
Signed-off-by: default avatarDaniel Golle <daniel@makrotopia.org>
Link: https://lore.kernel.org/r/8136eb5b2049177bc2f6d3e0f2aefecc342d626f.1674703830.git.daniel@makrotopia.org


Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
[sboyd@kernel.org: Add module license]
Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent a6473d0f

drivers/clk/mediatek/Kconfig

+17 −0
Original line number Diff line number Diff line
@@ -388,6 +388,23 @@ config COMMON_CLK_MT7629_HIFSYS 
	  This driver supports MediaTek MT7629 HIFSYS clocks providing

	  to PCI-E and USB.



config COMMON_CLK_MT7981

	bool "Clock driver for MediaTek MT7981"

	depends on ARCH_MEDIATEK || COMPILE_TEST

	select COMMON_CLK_MEDIATEK

	default ARCH_MEDIATEK

	help

	  This driver supports MediaTek MT7981 basic clocks and clocks

	  required for various peripherals found on this SoC.



config COMMON_CLK_MT7981_ETHSYS

	tristate "Clock driver for MediaTek MT7981 ETHSYS"

	depends on COMMON_CLK_MT7981

	default COMMON_CLK_MT7981

	help

	  This driver adds support for clocks for Ethernet and SGMII

	  required on MediaTek MT7981 SoC.



config COMMON_CLK_MT7986

	bool "Clock driver for MediaTek MT7986"

	depends on ARCH_MEDIATEK || COMPILE_TEST

drivers/clk/mediatek/Makefile

+4 −0
Original line number Diff line number Diff line
@@ -53,6 +53,10 @@ obj-$(CONFIG_COMMON_CLK_MT7622_AUDSYS) += clk-mt7622-aud.o 
obj-$(CONFIG_COMMON_CLK_MT7629) += clk-mt7629.o

obj-$(CONFIG_COMMON_CLK_MT7629_ETHSYS) += clk-mt7629-eth.o

obj-$(CONFIG_COMMON_CLK_MT7629_HIFSYS) += clk-mt7629-hif.o

obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-apmixed.o

obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-topckgen.o

obj-$(CONFIG_COMMON_CLK_MT7981) += clk-mt7981-infracfg.o

obj-$(CONFIG_COMMON_CLK_MT7981_ETHSYS) += clk-mt7981-eth.o

obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o

obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o

obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o

drivers/clk/mediatek/clk-mt7981-apmixed.c

0 → 100644
+102 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2021 MediaTek Inc.

 * Author: Sam Shih <sam.shih@mediatek.com>

 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>

 * Author: Jianhui Zhao <zhaojh329@gmail.com>

 * Author: Daniel Golle <daniel@makrotopia.org>

 */



#include <linux/clk-provider.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>



#include "clk-gate.h"

#include "clk-mtk.h"

#include "clk-mux.h"

#include "clk-pll.h"



#include <dt-bindings/clock/mediatek,mt7981-clk.h>

#include <linux/clk.h>



#define MT7981_PLL_FMAX (2500UL * MHZ)

#define CON0_MT7981_RST_BAR BIT(27)



#define PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \

		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift,         \

		 _div_table, _parent_name)                                     \

	{                                                                      \

		.id = _id, .name = _name, .reg = _reg, .pwr_reg = _pwr_reg,    \

		.en_mask = _en_mask, .flags = _flags,                          \

		.rst_bar_mask = CON0_MT7981_RST_BAR, .fmax = MT7981_PLL_FMAX,  \

		.pcwbits = _pcwbits, .pd_reg = _pd_reg, .pd_shift = _pd_shift, \

		.tuner_reg = _tuner_reg, .pcw_reg = _pcw_reg,                  \

		.pcw_shift = _pcw_shift, .div_table = _div_table,              \

		.parent_name = _parent_name,                                   \

	}



#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg,   \

	    _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift)                       \

	PLL_xtal(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,       \

		 _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, _pcw_shift, NULL,   \

		 "clkxtal")



static const struct mtk_pll_data plls[] = {

	PLL(CLK_APMIXED_ARMPLL, "armpll", 0x0200, 0x020C, 0x00000001, PLL_AO,

	    32, 0x0200, 4, 0, 0x0204, 0),

	PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0210, 0x021C, 0x00000001, 0, 32,

	    0x0210, 4, 0, 0x0214, 0),

	PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0220, 0x022C, 0x00000001, 0, 32,

	    0x0220, 4, 0, 0x0224, 0),

	PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0230, 0x023C, 0x00000001, 0, 32,

	    0x0230, 4, 0, 0x0234, 0),

	PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0240, 0x024C, 0x00000001, 0, 32,

	    0x0240, 4, 0, 0x0244, 0),

	PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0250, 0x025C, 0x00000001, 0, 32,

	    0x0250, 4, 0, 0x0254, 0),

	PLL(CLK_APMIXED_MPLL, "mpll", 0x0260, 0x0270, 0x00000001, 0, 32,

	    0x0260, 4, 0, 0x0264, 0),

	PLL(CLK_APMIXED_APLL2, "apll2", 0x0278, 0x0288, 0x00000001, 0, 32,

	    0x0278, 4, 0, 0x027C, 0),

};



static const struct of_device_id of_match_clk_mt7981_apmixed[] = {

	{ .compatible = "mediatek,mt7981-apmixedsys", },

	{ /* sentinel */ }

};



static int clk_mt7981_apmixed_probe(struct platform_device *pdev)

{

	struct clk_hw_onecell_data *clk_data;

	struct device_node *node = pdev->dev.of_node;

	int r;



	clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));

	if (!clk_data)

		return -ENOMEM;



	mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);



	r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);

	if (r) {

		pr_err("%s(): could not register clock provider: %d\n",

		       __func__, r);

		goto free_apmixed_data;

	}

	return r;



free_apmixed_data:

	mtk_free_clk_data(clk_data);

	return r;

}



static struct platform_driver clk_mt7981_apmixed_drv = {

	.probe = clk_mt7981_apmixed_probe,

	.driver = {

		.name = "clk-mt7981-apmixed",

		.of_match_table = of_match_clk_mt7981_apmixed,

	},

};

builtin_platform_driver(clk_mt7981_apmixed_drv);

drivers/clk/mediatek/clk-mt7981-eth.c

0 → 100644
+118 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2021 MediaTek Inc.

 * Author: Sam Shih <sam.shih@mediatek.com>

 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>

 * Author: Jianhui Zhao <zhaojh329@gmail.com>

 * Author: Daniel Golle <daniel@makrotopia.org>

 */



#include <linux/clk-provider.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>



#include "clk-mtk.h"

#include "clk-gate.h"



#include <dt-bindings/clock/mediatek,mt7981-clk.h>



static const struct mtk_gate_regs sgmii0_cg_regs = {

	.set_ofs = 0xE4,

	.clr_ofs = 0xE4,

	.sta_ofs = 0xE4,

};



#define GATE_SGMII0(_id, _name, _parent, _shift) {	\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &sgmii0_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\

	}



static const struct mtk_gate sgmii0_clks[] __initconst = {

	GATE_SGMII0(CLK_SGM0_TX_EN, "sgm0_tx_en", "usb_tx250m", 2),

	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", "usb_eq_rx250m", 3),

	GATE_SGMII0(CLK_SGM0_CK0_EN, "sgm0_ck0_en", "usb_ln0", 4),

	GATE_SGMII0(CLK_SGM0_CDR_CK0_EN, "sgm0_cdr_ck0_en", "usb_cdr", 5),

};



static const struct mtk_gate_regs sgmii1_cg_regs = {

	.set_ofs = 0xE4,

	.clr_ofs = 0xE4,

	.sta_ofs = 0xE4,

};



#define GATE_SGMII1(_id, _name, _parent, _shift) {	\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &sgmii1_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\

	}



static const struct mtk_gate sgmii1_clks[] __initconst = {

	GATE_SGMII1(CLK_SGM1_TX_EN, "sgm1_tx_en", "usb_tx250m", 2),

	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", "usb_eq_rx250m", 3),

	GATE_SGMII1(CLK_SGM1_CK1_EN, "sgm1_ck1_en", "usb_ln0", 4),

	GATE_SGMII1(CLK_SGM1_CDR_CK1_EN, "sgm1_cdr_ck1_en", "usb_cdr", 5),

};



static const struct mtk_gate_regs eth_cg_regs = {

	.set_ofs = 0x30,

	.clr_ofs = 0x30,

	.sta_ofs = 0x30,

};



#define GATE_ETH(_id, _name, _parent, _shift) {	\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &eth_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_no_setclr_inv,	\

	}



static const struct mtk_gate eth_clks[] __initconst = {

	GATE_ETH(CLK_ETH_FE_EN, "eth_fe_en", "netsys_2x", 6),

	GATE_ETH(CLK_ETH_GP2_EN, "eth_gp2_en", "sgm_325m", 7),

	GATE_ETH(CLK_ETH_GP1_EN, "eth_gp1_en", "sgm_325m", 8),

	GATE_ETH(CLK_ETH_WOCPU0_EN, "eth_wocpu0_en", "netsys_wed_mcu", 15),

};



static const struct mtk_clk_desc eth_desc = {

	.clks = eth_clks,

	.num_clks = ARRAY_SIZE(eth_clks),

};



static const struct mtk_clk_desc sgmii0_desc = {

	.clks = sgmii0_clks,

	.num_clks = ARRAY_SIZE(sgmii0_clks),

};



static const struct mtk_clk_desc sgmii1_desc = {

	.clks = sgmii1_clks,

	.num_clks = ARRAY_SIZE(sgmii1_clks),

};



static const struct of_device_id of_match_clk_mt7981_eth[] = {

	{ .compatible = "mediatek,mt7981-ethsys", .data = &eth_desc },

	{ .compatible = "mediatek,mt7981-sgmiisys_0", .data = &sgmii0_desc },

	{ .compatible = "mediatek,mt7981-sgmiisys_1", .data = &sgmii1_desc },

	{ /* sentinel */ }

};



static struct platform_driver clk_mt7981_eth_drv = {

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt7981-eth",

		.of_match_table = of_match_clk_mt7981_eth,

	},

};

module_platform_driver(clk_mt7981_eth_drv);

MODULE_LICENSE("GPL v2");

drivers/clk/mediatek/clk-mt7981-infracfg.c

0 → 100644
+207 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0

/*

 * Copyright (c) 2021 MediaTek Inc.

 * Author: Sam Shih <sam.shih@mediatek.com>

 * Author: Wenzhen Yu <wenzhen.yu@mediatek.com>

 * Author: Jianhui Zhao <zhaojh329@gmail.com>

 * Author: Daniel Golle <daniel@makrotopia.org>

 */



#include <linux/clk-provider.h>

#include <linux/of.h>

#include <linux/of_address.h>

#include <linux/of_device.h>

#include <linux/platform_device.h>

#include "clk-mtk.h"

#include "clk-gate.h"

#include "clk-mux.h"



#include <dt-bindings/clock/mediatek,mt7981-clk.h>

#include <linux/clk.h>



static DEFINE_SPINLOCK(mt7981_clk_lock);



static const struct mtk_fixed_factor infra_divs[] = {

	FACTOR(CLK_INFRA_66M_MCK, "infra_66m_mck", "sysaxi_sel", 1, 2),

};



static const char *const infra_uart_parent[] __initconst = { "csw_f26m_sel",

								"uart_sel" };



static const char *const infra_spi0_parents[] __initconst = { "i2c_sel",

							      "spi_sel" };



static const char *const infra_spi1_parents[] __initconst = { "i2c_sel",

							      "spim_mst_sel" };



static const char *const infra_pwm1_parents[] __initconst = { "pwm_sel" };



static const char *const infra_pwm_bsel_parents[] __initconst = {

	"cb_rtc_32p7k", "csw_f26m_sel", "infra_66m_mck", "pwm_sel"

};



static const char *const infra_pcie_parents[] __initconst = {

	"cb_rtc_32p7k", "csw_f26m_sel", "cb_cksq_40m", "pextp_tl_ck_sel"

};



static const struct mtk_mux infra_muxes[] = {

	/* MODULE_CLK_SEL_0 */

	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART0_SEL, "infra_uart0_sel",

			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 0, 1,

			     -1, -1, -1),

	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART1_SEL, "infra_uart1_sel",

			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 1, 1,

			     -1, -1, -1),

	MUX_GATE_CLR_SET_UPD(CLK_INFRA_UART2_SEL, "infra_uart2_sel",

			     infra_uart_parent, 0x0018, 0x0010, 0x0014, 2, 1,

			     -1, -1, -1),

	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI0_SEL, "infra_spi0_sel",

			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 4, 1,

			     -1, -1, -1),

	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI1_SEL, "infra_spi1_sel",

			     infra_spi1_parents, 0x0018, 0x0010, 0x0014, 5, 1,

			     -1, -1, -1),

	MUX_GATE_CLR_SET_UPD(CLK_INFRA_SPI2_SEL, "infra_spi2_sel",

			     infra_spi0_parents, 0x0018, 0x0010, 0x0014, 6, 1,

			     -1, -1, -1),

	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM1_SEL, "infra_pwm1_sel",

			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 9, 1,

			     -1, -1, -1),

	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM2_SEL, "infra_pwm2_sel",

			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 11, 1,

			     -1, -1, -1),

	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM3_SEL, "infra_pwm3_sel",

			     infra_pwm1_parents, 0x0018, 0x0010, 0x0014, 15, 1,

			     -1, -1, -1),

	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PWM_BSEL, "infra_pwm_bsel",

			     infra_pwm_bsel_parents, 0x0018, 0x0010, 0x0014, 13,

			     2, -1, -1, -1),

	/* MODULE_CLK_SEL_1 */

	MUX_GATE_CLR_SET_UPD(CLK_INFRA_PCIE_SEL, "infra_pcie_sel",

			     infra_pcie_parents, 0x0028, 0x0020, 0x0024, 0, 2,

			     -1, -1, -1),

};



static const struct mtk_gate_regs infra0_cg_regs = {

	.set_ofs = 0x40,

	.clr_ofs = 0x44,

	.sta_ofs = 0x48,

};



static const struct mtk_gate_regs infra1_cg_regs = {

	.set_ofs = 0x50,

	.clr_ofs = 0x54,

	.sta_ofs = 0x58,

};



static const struct mtk_gate_regs infra2_cg_regs = {

	.set_ofs = 0x60,

	.clr_ofs = 0x64,

	.sta_ofs = 0x68,

};



#define GATE_INFRA0(_id, _name, _parent, _shift)                               \

	{                                                                      \

		.id = _id, .name = _name, .parent_name = _parent,              \

		.regs = &infra0_cg_regs, .shift = _shift,                      \

		.ops = &mtk_clk_gate_ops_setclr,                               \

	}



#define GATE_INFRA1(_id, _name, _parent, _shift)                               \

	{                                                                      \

		.id = _id, .name = _name, .parent_name = _parent,              \

		.regs = &infra1_cg_regs, .shift = _shift,                      \

		.ops = &mtk_clk_gate_ops_setclr,                               \

	}



#define GATE_INFRA2(_id, _name, _parent, _shift)                               \

	{                                                                      \

		.id = _id, .name = _name, .parent_name = _parent,              \

		.regs = &infra2_cg_regs, .shift = _shift,                      \

		.ops = &mtk_clk_gate_ops_setclr,                               \

	}



static const struct mtk_gate infra_clks[] = {

	/* INFRA0 */

	GATE_INFRA0(CLK_INFRA_GPT_STA, "infra_gpt_sta", "infra_66m_mck", 0),

	GATE_INFRA0(CLK_INFRA_PWM_HCK, "infra_pwm_hck", "infra_66m_mck", 1),

	GATE_INFRA0(CLK_INFRA_PWM_STA, "infra_pwm_sta", "infra_pwm_bsel", 2),

	GATE_INFRA0(CLK_INFRA_PWM1_CK, "infra_pwm1", "infra_pwm1_sel", 3),

	GATE_INFRA0(CLK_INFRA_PWM2_CK, "infra_pwm2", "infra_pwm2_sel", 4),

	GATE_INFRA0(CLK_INFRA_CQ_DMA_CK, "infra_cq_dma", "sysaxi", 6),



	GATE_INFRA0(CLK_INFRA_AUD_BUS_CK, "infra_aud_bus", "sysaxi", 8),

	GATE_INFRA0(CLK_INFRA_AUD_26M_CK, "infra_aud_26m", "csw_f26m_sel", 9),

	GATE_INFRA0(CLK_INFRA_AUD_L_CK, "infra_aud_l", "aud_l", 10),

	GATE_INFRA0(CLK_INFRA_AUD_AUD_CK, "infra_aud_aud", "a1sys", 11),

	GATE_INFRA0(CLK_INFRA_AUD_EG2_CK, "infra_aud_eg2", "a_tuner", 13),

	GATE_INFRA0(CLK_INFRA_DRAMC_26M_CK, "infra_dramc_26m", "csw_f26m_sel",

		    14),

	GATE_INFRA0(CLK_INFRA_DBG_CK, "infra_dbg", "infra_66m_mck", 15),

	GATE_INFRA0(CLK_INFRA_AP_DMA_CK, "infra_ap_dma", "infra_66m_mck", 16),

	GATE_INFRA0(CLK_INFRA_SEJ_CK, "infra_sej", "infra_66m_mck", 24),

	GATE_INFRA0(CLK_INFRA_SEJ_13M_CK, "infra_sej_13m", "csw_f26m_sel", 25),

	GATE_INFRA0(CLK_INFRA_PWM3_CK, "infra_pwm3", "infra_pwm3_sel", 27),

	/* INFRA1 */

	GATE_INFRA1(CLK_INFRA_THERM_CK, "infra_therm", "csw_f26m_sel", 0),

	GATE_INFRA1(CLK_INFRA_I2C0_CK, "infra_i2c0", "i2c_bck", 1),

	GATE_INFRA1(CLK_INFRA_UART0_CK, "infra_uart0", "infra_uart0_sel", 2),

	GATE_INFRA1(CLK_INFRA_UART1_CK, "infra_uart1", "infra_uart1_sel", 3),

	GATE_INFRA1(CLK_INFRA_UART2_CK, "infra_uart2", "infra_uart2_sel", 4),

	GATE_INFRA1(CLK_INFRA_SPI2_CK, "infra_spi2", "infra_spi2_sel", 6),

	GATE_INFRA1(CLK_INFRA_SPI2_HCK_CK, "infra_spi2_hck", "infra_66m_mck", 7),

	GATE_INFRA1(CLK_INFRA_NFI1_CK, "infra_nfi1", "nfi1x", 8),

	GATE_INFRA1(CLK_INFRA_SPINFI1_CK, "infra_spinfi1", "spinfi_bck", 9),

	GATE_INFRA1(CLK_INFRA_NFI_HCK_CK, "infra_nfi_hck", "infra_66m_mck", 10),

	GATE_INFRA1(CLK_INFRA_SPI0_CK, "infra_spi0", "infra_spi0_sel", 11),

	GATE_INFRA1(CLK_INFRA_SPI1_CK, "infra_spi1", "infra_spi1_sel", 12),

	GATE_INFRA1(CLK_INFRA_SPI0_HCK_CK, "infra_spi0_hck", "infra_66m_mck",

		    13),

	GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",

		    14),

	GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15),

	GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16),

	GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17),

	GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18),

	GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19),

	GATE_INFRA1(CLK_INFRA_ADC_26M_CK, "infra_adc_26m", "infra_adc_frc", 20),

	GATE_INFRA1(CLK_INFRA_ADC_FRC_CK, "infra_adc_frc", "csw_f26m", 21),

	GATE_INFRA1(CLK_INFRA_FBIST2FPC_CK, "infra_fbist2fpc", "nfi1x", 23),

	GATE_INFRA1(CLK_INFRA_I2C_MCK_CK, "infra_i2c_mck", "sysaxi", 25),

	GATE_INFRA1(CLK_INFRA_I2C_PCK_CK, "infra_i2c_pck", "infra_66m_mck", 26),

	/* INFRA2 */

	GATE_INFRA2(CLK_INFRA_IUSB_133_CK, "infra_iusb_133", "sysaxi", 0),

	GATE_INFRA2(CLK_INFRA_IUSB_66M_CK, "infra_iusb_66m", "sysaxi", 1),

	GATE_INFRA2(CLK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", "u2u3_sys", 2),

	GATE_INFRA2(CLK_INFRA_IUSB_CK, "infra_iusb", "u2u3_ref", 3),

	GATE_INFRA2(CLK_INFRA_IPCIE_CK, "infra_ipcie", "pextp_tl", 12),

	GATE_INFRA2(CLK_INFRA_IPCIE_PIPE_CK, "infra_ipcie_pipe", "cb_cksq_40m",

		    13),

	GATE_INFRA2(CLK_INFRA_IPCIER_CK, "infra_ipcier", "csw_f26m", 14),

	GATE_INFRA2(CLK_INFRA_IPCIEB_CK, "infra_ipcieb", "sysaxi", 15),

};



static const struct mtk_clk_desc infracfg_desc = {

	.factor_clks = infra_divs,

	.num_factor_clks = ARRAY_SIZE(infra_divs),

	.mux_clks = infra_muxes,

	.num_mux_clks = ARRAY_SIZE(infra_muxes),

	.clks = infra_clks,

	.num_clks = ARRAY_SIZE(infra_clks),

	.clk_lock = &mt7981_clk_lock,

};



static const struct of_device_id of_match_clk_mt7981_infracfg[] = {

	{ .compatible = "mediatek,mt7981-infracfg", .data = &infracfg_desc },

	{ /* sentinel */ }

};



static struct platform_driver clk_mt7981_infracfg_drv = {

	.probe = mtk_clk_simple_probe,

	.remove = mtk_clk_simple_remove,

	.driver = {

		.name = "clk-mt7981-infracfg",

		.of_match_table = of_match_clk_mt7981_infracfg,

	},

};

builtin_platform_driver(clk_mt7981_infracfg_drv);