Commit 812bae32 authored by Zev Weiss's avatar Zev Weiss Committed by Joel Stanley
Browse files

ARM: dts: aspeed: Update e3c246d4i vuart properties 



This device-tree was merged with a provisional vuart IRQ-polarity
property that was still under review and ended up taking a somewhat
different form.  This patch updates it to match the final form of the
new vuart properties, which additionally allow specifying the SIRQ
number and LPC address.

Signed-off-by: default avatarZev Weiss <zev@bewilderbeest.net>
Reviewed-by: default avatarAndrew Jeffery <andrew@aj.id.au>
Fixes: ca03042f ("serial: 8250_aspeed_vuart: add aspeed, lpc-io-reg and aspeed, lpc-interrupts DT properties")
Reviewed-by: default avatarJoel Stanley <joel@jms.id.au>
Link: https://lore.kernel.org/r/20210416075113.18047-1-zev@bewilderbeest.net


Signed-off-by: default avatarJoel Stanley <joel@jms.id.au>
parent ca46ad22

arch/arm/boot/dts/aspeed-bmc-asrock-e3c246d4i.dts

+3 −1
Original line number Diff line number Diff line
@@ -4,6 +4,7 @@ 
#include "aspeed-g5.dtsi"

#include <dt-bindings/gpio/aspeed-gpio.h>

#include <dt-bindings/i2c/i2c.h>

#include <dt-bindings/interrupt-controller/irq.h>



/{

	model = "ASRock E3C246D4I BMC";
@@ -73,7 +74,8 @@ 


&vuart {

	status = "okay";

	aspeed,sirq-active-high;

	aspeed,lpc-io-reg = <0x2f8>;

	aspeed,lpc-interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;

};



&mac0 {