Commit 80fe155b authored by Ben Skeggs's avatar Ben Skeggs
Browse files

drm/nvc0/dmaobj: implement initial bind() method 



Currently unused.

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent f756944a

drivers/gpu/drm/nouveau/core/engine/dmaobj/nvc0.c

+58 −1
Original line number Diff line number Diff line
@@ -39,7 +39,9 @@ nvc0_dmaobj_bind(struct nouveau_dmaeng *dmaeng, 
		 struct nouveau_dmaobj *dmaobj,

		 struct nouveau_gpuobj **pgpuobj)

{

	int ret = 0;

	u32 flags0 = nv_mclass(dmaobj);

	u32 flags5 = 0x00000000;

	int ret;



	if (!nv_iclass(parent, NV_ENGCTX_CLASS)) {

		switch (nv_mclass(parent->parent)) {
@@ -49,6 +51,61 @@ nvc0_dmaobj_bind(struct nouveau_dmaeng *dmaeng, 
	} else

		return 0;



	if (!(dmaobj->conf0 & NVC0_DMA_CONF0_ENABLE)) {

		if (dmaobj->target == NV_MEM_TARGET_VM) {

			dmaobj->conf0  = NVC0_DMA_CONF0_PRIV_VM;

			dmaobj->conf0 |= NVC0_DMA_CONF0_TYPE_VM;

		} else {

			dmaobj->conf0  = NVC0_DMA_CONF0_PRIV_US;

			dmaobj->conf0 |= NVC0_DMA_CONF0_TYPE_LINEAR;

			dmaobj->conf0 |= 0x00020000;

		}

	}



	flags0 |= (dmaobj->conf0 & NVC0_DMA_CONF0_TYPE) << 22;

	flags0 |= (dmaobj->conf0 & NVC0_DMA_CONF0_PRIV);

	flags5 |= (dmaobj->conf0 & NVC0_DMA_CONF0_UNKN);



	switch (dmaobj->target) {

	case NV_MEM_TARGET_VM:

		flags0 |= 0x00000000;

		break;

	case NV_MEM_TARGET_VRAM:

		flags0 |= 0x00010000;

		break;

	case NV_MEM_TARGET_PCI:

		flags0 |= 0x00020000;

		break;

	case NV_MEM_TARGET_PCI_NOSNOOP:

		flags0 |= 0x00030000;

		break;

	default:

		return -EINVAL;

	}



	switch (dmaobj->access) {

	case NV_MEM_ACCESS_VM:

		break;

	case NV_MEM_ACCESS_RO:

		flags0 |= 0x00040000;

		break;

	case NV_MEM_ACCESS_WO:

	case NV_MEM_ACCESS_RW:

		flags0 |= 0x00080000;

		break;

	}



	ret = nouveau_gpuobj_new(parent, parent, 24, 32, 0, pgpuobj);

	if (ret == 0) {

		nv_wo32(*pgpuobj, 0x00, flags0);

		nv_wo32(*pgpuobj, 0x04, lower_32_bits(dmaobj->limit));

		nv_wo32(*pgpuobj, 0x08, lower_32_bits(dmaobj->start));

		nv_wo32(*pgpuobj, 0x0c, upper_32_bits(dmaobj->limit) << 24 |

					upper_32_bits(dmaobj->start));

		nv_wo32(*pgpuobj, 0x10, 0x00000000);

		nv_wo32(*pgpuobj, 0x14, flags5);

	}



	return ret;

}

drivers/gpu/drm/nouveau/core/include/core/class.h

+11 −0
Original line number Diff line number Diff line
@@ -69,6 +69,17 @@ struct nv_device_class { 
#define NV50_DMA_CONF0_TYPE_LINEAR                                   0x00000000

#define NV50_DMA_CONF0_TYPE_VM                                       0x0000007f



/* NVC0:NVD9 */

#define NVC0_DMA_CONF0_ENABLE                                        0x80000000

#define NVC0_DMA_CONF0_PRIV                                          0x00300000

#define NVC0_DMA_CONF0_PRIV_VM                                       0x00000000

#define NVC0_DMA_CONF0_PRIV_US                                       0x00100000

#define NVC0_DMA_CONF0_PRIV__S                                       0x00200000

#define NVC0_DMA_CONF0_UNKN /* PART? */                              0x00030000

#define NVC0_DMA_CONF0_TYPE                                          0x000000ff

#define NVC0_DMA_CONF0_TYPE_LINEAR                                   0x00000000

#define NVC0_DMA_CONF0_TYPE_VM                                       0x000000ff



struct nv_dma_class {

	u32 flags;

	u32 pad0;