Commit 80fb55a9 authored by John Crispin's avatar John Crispin Committed by Ralf Baechle
Browse files

MIPS: ralink: adds support for RT2880 SoC family 



Add support code for rt2880 SOC.

The code detects the SoC and registers the clk / pinmux settings.

Signed-off-by: default avatarJohn Crispin <blogic@openwrt.org>
Signed-off-by: default avatarGabor Juhos <juhosg@openwrt.org>
Patchwork: http://patchwork.linux-mips.org/patch/5176/
parent eb63875c

arch/mips/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -1144,7 +1144,7 @@ config BOOT_ELF32 


config MIPS_L1_CACHE_SHIFT

	int

	default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL

	default "4" if MACH_DECSTATION || MIKROTIK_RB532 || PMC_MSP4200_EVAL || SOC_RT288X

	default "6" if MIPS_CPU_SCACHE

	default "7" if SGI_IP22 || SGI_IP27 || SGI_IP28 || SNI_RM || CPU_CAVIUM_OCTEON

	default "5"

arch/mips/include/asm/mach-ralink/rt288x.h

0 → 100644
+49 −0
Original line number Diff line number Diff line 
/*

 * This program is free software; you can redistribute it and/or modify it

 * under the terms of the GNU General Public License version 2 as published

 * by the Free Software Foundation.

 *

 * Parts of this file are based on Ralink's 2.6.21 BSP

 *

 * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>

 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>

 * Copyright (C) 2013 John Crispin <blogic@openwrt.org>

 */



#ifndef _RT288X_REGS_H_

#define _RT288X_REGS_H_



#define RT2880_SYSC_BASE		0x00300000



#define SYSC_REG_CHIP_NAME0		0x00

#define SYSC_REG_CHIP_NAME1		0x04

#define SYSC_REG_CHIP_ID		0x0c

#define SYSC_REG_SYSTEM_CONFIG		0x10

#define SYSC_REG_CLKCFG			0x30



#define RT2880_CHIP_NAME0		0x38325452

#define RT2880_CHIP_NAME1		0x20203038



#define CHIP_ID_ID_MASK			0xff

#define CHIP_ID_ID_SHIFT		8

#define CHIP_ID_REV_MASK		0xff



#define SYSTEM_CONFIG_CPUCLK_SHIFT	20

#define SYSTEM_CONFIG_CPUCLK_MASK	0x3

#define SYSTEM_CONFIG_CPUCLK_250	0x0

#define SYSTEM_CONFIG_CPUCLK_266	0x1

#define SYSTEM_CONFIG_CPUCLK_280	0x2

#define SYSTEM_CONFIG_CPUCLK_300	0x3



#define RT2880_GPIO_MODE_I2C		BIT(0)

#define RT2880_GPIO_MODE_UART0		BIT(1)

#define RT2880_GPIO_MODE_SPI		BIT(2)

#define RT2880_GPIO_MODE_UART1		BIT(3)

#define RT2880_GPIO_MODE_JTAG		BIT(4)

#define RT2880_GPIO_MODE_MDIO		BIT(5)

#define RT2880_GPIO_MODE_SDRAM		BIT(6)

#define RT2880_GPIO_MODE_PCI		BIT(7)



#define CLKCFG_SRAM_CS_N_WDT		BIT(9)



#endif

arch/mips/ralink/Kconfig

+3 −0
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@@ -6,6 +6,9 @@ choice 
	help

	  Select Ralink MIPS SoC type.



	config SOC_RT288X

		bool "RT288x"



	config SOC_RT305X

		bool "RT305x"

		select USB_ARCH_HAS_HCD

arch/mips/ralink/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -8,6 +8,7 @@ 


obj-y := prom.o of.o reset.o clk.o irq.o



obj-$(CONFIG_SOC_RT288X) += rt288x.o

obj-$(CONFIG_SOC_RT305X) += rt305x.o



obj-$(CONFIG_EARLY_PRINTK) += early_printk.o

arch/mips/ralink/Platform

+5 −0
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@@ -4,6 +4,11 @@ 
core-$(CONFIG_RALINK)		+= arch/mips/ralink/

cflags-$(CONFIG_RALINK)		+= -I$(srctree)/arch/mips/include/asm/mach-ralink



#

# Ralink RT288x

#

load-$(CONFIG_SOC_RT288X)	+= 0xffffffff88000000



#

# Ralink RT305x

#