Commit 80ed77f9 authored by yipechai's avatar yipechai Committed by Alex Deucher
Browse files

drm/amdgpu: Optimize amdgpu_nbio_ras_late_init/amdgpu_nbio_ras_fini function code 



Optimize amdgpu_nbio_ras_late_init/amdgpu_nbio_ras_fini function code.

Signed-off-by: default avataryipechai <YiPeng.Chai@amd.com>
Reviewed-by: default avatarTao Zhou <tao.zhou1@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent cb9561d0

drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.c

+5 −35
Original line number Diff line number Diff line
@@ -25,26 +25,9 @@ 
int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, void *ras_info)

{

	int r;

	struct ras_ih_if ih_info = {

		.cb = NULL,

	};

	struct ras_fs_if fs_info = {

		.sysfs_name = "pcie_bif_err_count",

	};



	if (!adev->nbio.ras_if) {

		adev->nbio.ras_if = kmalloc(sizeof(struct ras_common_if), GFP_KERNEL);

		if (!adev->nbio.ras_if)

			return -ENOMEM;

		adev->nbio.ras_if->block = AMDGPU_RAS_BLOCK__PCIE_BIF;

		adev->nbio.ras_if->type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE;

		adev->nbio.ras_if->sub_block_index = 0;

	}

	ih_info.head = fs_info.head = *adev->nbio.ras_if;

	r = amdgpu_ras_late_init(adev, adev->nbio.ras_if,

				 &fs_info, &ih_info);

	r = amdgpu_ras_block_late_init(adev, adev->nbio.ras_if);

	if (r)

		goto free;

		return r;



	if (amdgpu_ras_is_supported(adev, adev->nbio.ras_if->block)) {

		r = amdgpu_irq_get(adev, &adev->nbio.ras_controller_irq, 0);
@@ -53,30 +36,17 @@ int amdgpu_nbio_ras_late_init(struct amdgpu_device *adev, void *ras_info) 
		r = amdgpu_irq_get(adev, &adev->nbio.ras_err_event_athub_irq, 0);

		if (r)

			goto late_fini;

	} else {

		r = 0;

		goto free;

	}



	return 0;

late_fini:

	amdgpu_ras_late_fini(adev, adev->nbio.ras_if, &ih_info);

free:

	kfree(adev->nbio.ras_if);

	adev->nbio.ras_if = NULL;

	amdgpu_ras_block_late_fini(adev, adev->nbio.ras_if);

	return r;

}



void amdgpu_nbio_ras_fini(struct amdgpu_device *adev)

{

	if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__PCIE_BIF) &&

			adev->nbio.ras_if) {

		struct ras_common_if *ras_if = adev->nbio.ras_if;

		struct ras_ih_if ih_info = {

			.cb = NULL,

		};



		amdgpu_ras_late_fini(adev, ras_if, &ih_info);

		kfree(ras_if);

	}

			adev->nbio.ras_if)

		amdgpu_ras_block_late_fini(adev, adev->nbio.ras_if);

}

drivers/gpu/drm/amd/amdgpu/amdgpu_ras.c

+1 −0
Original line number Diff line number Diff line
@@ -2301,6 +2301,7 @@ int amdgpu_ras_init(struct amdgpu_device *adev) 
		if (!adev->gmc.xgmi.connected_to_cpu) {

			adev->nbio.ras = &nbio_v7_4_ras;

			amdgpu_ras_register_ras_block(adev, &adev->nbio.ras->ras_block);

			adev->nbio.ras_if = &adev->nbio.ras->ras_block.ras_comm;

		}

		break;

	default:

drivers/gpu/drm/amd/amdgpu/nbio_v7_4.c

+1 −0
Original line number Diff line number Diff line
@@ -667,6 +667,7 @@ struct amdgpu_nbio_ras nbio_v7_4_ras = { 
		.ras_comm = {

			.name = "pcie_bif",

			.block = AMDGPU_RAS_BLOCK__PCIE_BIF,

			.type = AMDGPU_RAS_ERROR__MULTI_UNCORRECTABLE,

		},

		.hw_ops = &nbio_v7_4_ras_hw_ops,

		.ras_late_init = amdgpu_nbio_ras_late_init,