Loading drivers/clk/clk-qoriq.c +41 −0 Original line number Diff line number Diff line Loading @@ -266,6 +266,31 @@ static const struct clockgen_muxinfo ls1043a_hwa2 = { }, }; static const struct clockgen_muxinfo ls1046a_hwa1 = { { {}, {}, { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, }, }; static const struct clockgen_muxinfo ls1046a_hwa2 = { { {}, { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, {}, {}, { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, }, }; static const struct clockgen_muxinfo t1023_hwa1 = { { {}, Loading Loading @@ -488,6 +513,21 @@ static const struct clockgen_chipinfo chipinfo[] = { .pll_mask = 0x07, .flags = CG_PLL_8BIT, }, { .compat = "fsl,ls1046a-clockgen", .init_periph = t2080_init_periph, .cmux_groups = { &t1040_cmux }, .hwaccel = { &ls1046a_hwa1, &ls1046a_hwa2 }, .cmux_to_group = { 0, -1 }, .pll_mask = 0x07, .flags = CG_PLL_8BIT, }, { .compat = "fsl,ls2080a-clockgen", .cmux_groups = { Loading Loading @@ -1272,6 +1312,7 @@ CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init); /* Legacy nodes */ Loading Loading
drivers/clk/clk-qoriq.c +41 −0 Original line number Diff line number Diff line Loading @@ -266,6 +266,31 @@ static const struct clockgen_muxinfo ls1043a_hwa2 = { }, }; static const struct clockgen_muxinfo ls1046a_hwa1 = { { {}, {}, { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, }, }; static const struct clockgen_muxinfo ls1046a_hwa2 = { { {}, { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, {}, {}, { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, }, }; static const struct clockgen_muxinfo t1023_hwa1 = { { {}, Loading Loading @@ -488,6 +513,21 @@ static const struct clockgen_chipinfo chipinfo[] = { .pll_mask = 0x07, .flags = CG_PLL_8BIT, }, { .compat = "fsl,ls1046a-clockgen", .init_periph = t2080_init_periph, .cmux_groups = { &t1040_cmux }, .hwaccel = { &ls1046a_hwa1, &ls1046a_hwa2 }, .cmux_to_group = { 0, -1 }, .pll_mask = 0x07, .flags = CG_PLL_8BIT, }, { .compat = "fsl,ls2080a-clockgen", .cmux_groups = { Loading Loading @@ -1272,6 +1312,7 @@ CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qoriq-clockgen-1.0", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init); CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init); /* Legacy nodes */ Loading