Commit 80e30368 authored by Rafael J. Wysocki's avatar Rafael J. Wysocki
Browse files

Merge back cpufreq material for v5.9.

parents 39a188b8 7aa10312

Documentation/admin-guide/kernel-parameters.txt

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@@ -703,6 +703,11 @@ 
	cpufreq.off=1	[CPU_FREQ]

			disable the cpufreq sub-system



	cpufreq.default_governor=

			[CPU_FREQ] Name of the default cpufreq governor or

			policy to use. This governor must be registered in the

			kernel before the cpufreq driver probes.



	cpu_init_udelay=N

			[X86] Delay for N microsec between assert and de-assert

			of APIC INIT to start processors.  This delay occurs

Documentation/admin-guide/pm/cpufreq.rst

+3 −3
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@@ -147,9 +147,9 @@ CPUs in it. 


The next major initialization step for a new policy object is to attach a

scaling governor to it (to begin with, that is the default scaling governor

determined by the kernel configuration, but it may be changed later

via ``sysfs``).  First, a pointer to the new policy object is passed to the

governor's ``->init()`` callback which is expected to initialize all of the

determined by the kernel command line or configuration, but it may be changed

later via ``sysfs``).  First, a pointer to the new policy object is passed to

the governor's ``->init()`` callback which is expected to initialize all of the

data structures necessary to handle the given policy and, possibly, to add

a governor ``sysfs`` interface to it.  Next, the governor is started by

invoking its ``->start()`` callback.

Documentation/admin-guide/pm/intel_pstate.rst

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@@ -431,6 +431,17 @@ argument is passed to the kernel in the command line. 
	supported in the current configuration, writes to this attribute will

	fail with an appropriate error.



``energy_efficiency``

	This attribute is only present on platforms, which have CPUs matching

	Kaby Lake or Coffee Lake desktop CPU model. By default

	energy efficiency optimizations are disabled on these CPU models in HWP

	mode by this driver. Enabling energy efficiency may limit maximum

	operating frequency in both HWP and non HWP mode. In non HWP mode,

	optimizations are done only in the turbo frequency range. In HWP mode,

	optimizations are done in the entire frequency range. Setting this

	attribute to "1" enables energy efficiency optimizations and setting

	to "0" disables energy efficiency optimizations.



Interpretation of Policy Attributes

-----------------------------------
@@ -554,7 +565,11 @@ somewhere between the two extremes: 
Strings written to the ``energy_performance_preference`` attribute are

internally translated to integer values written to the processor's

Energy-Performance Preference (EPP) knob (if supported) or its

Energy-Performance Bias (EPB) knob.

Energy-Performance Bias (EPB) knob. It is also possible to write a positive

integer value between 0 to 255, if the EPP feature is present. If the EPP

feature is not present, writing integer value to this attribute is not

supported. In this case, user can use

 "/sys/devices/system/cpu/cpu*/power/energy_perf_bias" interface.



[Note that tasks may by migrated from one CPU to another by the scheduler's

load-balancing algorithm and if different energy vs performance hints are

arch/powerpc/platforms/cell/cpufreq_spudemand.c

+2 −24
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@@ -126,30 +126,8 @@ static struct cpufreq_governor spu_governor = { 
	.stop = spu_gov_stop,

	.owner = THIS_MODULE,

};



/*

 * module init and destoy

 */



static int __init spu_gov_init(void)

{

	int ret;



	ret = cpufreq_register_governor(&spu_governor);

	if (ret)

		printk(KERN_ERR "registration of governor failed\n");

	return ret;

}



static void __exit spu_gov_exit(void)

{

	cpufreq_unregister_governor(&spu_governor);

}





module_init(spu_gov_init);

module_exit(spu_gov_exit);

cpufreq_governor_init(spu_governor);

cpufreq_governor_exit(spu_governor);



MODULE_LICENSE("GPL");

MODULE_AUTHOR("Christian Krafft <krafft@de.ibm.com>");

arch/x86/include/asm/msr-index.h

+4 −2
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@@ -149,6 +149,10 @@ 


#define MSR_LBR_SELECT			0x000001c8

#define MSR_LBR_TOS			0x000001c9



#define MSR_IA32_POWER_CTL		0x000001fc

#define MSR_IA32_POWER_CTL_BIT_EE	19



#define MSR_LBR_NHM_FROM		0x00000680

#define MSR_LBR_NHM_TO			0x000006c0

#define MSR_LBR_CORE_FROM		0x00000040
@@ -253,8 +257,6 @@ 


#define MSR_PEBS_FRONTEND		0x000003f7



#define MSR_IA32_POWER_CTL		0x000001fc



#define MSR_IA32_MC0_CTL		0x00000400

#define MSR_IA32_MC0_STATUS		0x00000401

#define MSR_IA32_MC0_ADDR		0x00000402