Commit 80d69185 authored by Allen-KH Cheng's avatar Allen-KH Cheng Committed by Bjorn Andersson
Browse files

remoteproc: mediatek: Support mt8186 scp 



Add SCP support for mt8186

Signed-off-by: default avatarAllen-KH Cheng <Allen-KH.Cheng@mediatek.com>
Reviewed-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220225132747.31808-3-allen-kh.cheng@mediatek.com
parent 22335385

drivers/remoteproc/mtk_common.h

+3 −0
Original line number Diff line number Diff line
@@ -32,6 +32,9 @@ 
#define MT8183_SCP_CACHESIZE_8KB	BIT(8)

#define MT8183_SCP_CACHE_CON_WAYEN	BIT(10)



#define MT8186_SCP_L1_SRAM_PD_P1	0x40B0

#define MT8186_SCP_L1_SRAM_PD_p2	0x40B4



#define MT8192_L2TCM_SRAM_PD_0		0x10C0

#define MT8192_L2TCM_SRAM_PD_1		0x10C4

#define MT8192_L2TCM_SRAM_PD_2		0x10C8

drivers/remoteproc/mtk_scp.c

+35 −0
Original line number Diff line number Diff line
@@ -383,6 +383,27 @@ static void mt8192_power_off_sram(void __iomem *addr) 
		writel(GENMASK(i, 0), addr);

}



static int mt8186_scp_before_load(struct mtk_scp *scp)

{

	/* Clear SCP to host interrupt */

	writel(MT8183_SCP_IPC_INT_BIT, scp->reg_base + MT8183_SCP_TO_HOST);



	/* Reset clocks before loading FW */

	writel(0x0, scp->reg_base + MT8183_SCP_CLK_SW_SEL);

	writel(0x0, scp->reg_base + MT8183_SCP_CLK_DIV_SEL);



	/* Turn on the power of SCP's SRAM before using it. Enable 1 block per time*/

	mt8192_power_on_sram(scp->reg_base + MT8183_SCP_SRAM_PDN);



	/* Initialize TCM before loading FW. */

	writel(0x0, scp->reg_base + MT8183_SCP_L1_SRAM_PD);

	writel(0x0, scp->reg_base + MT8183_SCP_TCM_TAIL_SRAM_PD);

	writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_P1);

	writel(0x0, scp->reg_base + MT8186_SCP_L1_SRAM_PD_p2);



	return 0;

}



static int mt8192_scp_before_load(struct mtk_scp *scp)

{

	/* clear SPM interrupt, SCP2SPM_IPC_CLR */
@@ -874,6 +895,19 @@ static const struct mtk_scp_of_data mt8183_of_data = { 
	.ipi_buf_offset = 0x7bdb0,

};



static const struct mtk_scp_of_data mt8186_of_data = {

	.scp_clk_get = mt8195_scp_clk_get,

	.scp_before_load = mt8186_scp_before_load,

	.scp_irq_handler = mt8183_scp_irq_handler,

	.scp_reset_assert = mt8183_scp_reset_assert,

	.scp_reset_deassert = mt8183_scp_reset_deassert,

	.scp_stop = mt8183_scp_stop,

	.scp_da_to_va = mt8183_scp_da_to_va,

	.host_to_scp_reg = MT8183_HOST_TO_SCP,

	.host_to_scp_int_bit = MT8183_HOST_IPC_INT_BIT,

	.ipi_buf_offset = 0x7bdb0,

};



static const struct mtk_scp_of_data mt8192_of_data = {

	.scp_clk_get = mt8192_scp_clk_get,

	.scp_before_load = mt8192_scp_before_load,
@@ -900,6 +934,7 @@ static const struct mtk_scp_of_data mt8195_of_data = { 


static const struct of_device_id mtk_scp_of_match[] = {

	{ .compatible = "mediatek,mt8183-scp", .data = &mt8183_of_data },

	{ .compatible = "mediatek,mt8186-scp", .data = &mt8186_of_data },

	{ .compatible = "mediatek,mt8192-scp", .data = &mt8192_of_data },

	{ .compatible = "mediatek,mt8195-scp", .data = &mt8195_of_data },

	{},