Commit 80ca7765 authored by Vinod Koul's avatar Vinod Koul Committed by Stephen Boyd
Browse files

clk: qcom: clk-alpha-pll: modularize alpha_pll_trion_set_rate() 



Trion 5LPE set rate uses code similar to alpha_pll_trion_set_rate() but
with different registers. Modularize these by moving out latch and latch
ack bits so that we can reuse the function.

Suggested-by: default avatarAngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Reviewed-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20210127070811.152690-3-vkoul@kernel.org


Signed-off-by: default avatarStephen Boyd <sboyd@kernel.org>
parent 160210b4

drivers/clk/qcom/clk-alpha-pll.c

+11 −7
Original line number Diff line number Diff line
@@ -1471,8 +1471,8 @@ static int alpha_pll_lucid_prepare(struct clk_hw *hw) 
	return __alpha_pll_trion_prepare(hw, LUCID_PCAL_DONE);

}



static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,

				    unsigned long prate)

static int __alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,

				      unsigned long prate, u32 latch_bit, u32 latch_ack)

{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	unsigned long rrate;
@@ -1490,22 +1490,20 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 
	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);



	/* Latch the PLL input */

	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),

				 PLL_UPDATE, PLL_UPDATE);

	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, latch_bit);

	if (ret)

		return ret;



	/* Wait for 2 reference cycles before checking the ACK bit. */

	udelay(1);

	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &val);

	if (!(val & ALPHA_PLL_ACK_LATCH)) {

	if (!(val & latch_ack)) {

		pr_err("Lucid PLL latch failed. Output may be unstable!\n");

		return -EINVAL;

	}



	/* Return the latch input to 0 */

	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),

				 PLL_UPDATE, 0);

	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll), latch_bit, 0);

	if (ret)

		return ret;
@@ -1520,6 +1518,12 @@ static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate, 
	return 0;

}



static int alpha_pll_trion_set_rate(struct clk_hw *hw, unsigned long rate,

				    unsigned long prate)

{

	return __alpha_pll_trion_set_rate(hw, rate, prate, PLL_UPDATE, ALPHA_PLL_ACK_LATCH);

}



const struct clk_ops clk_alpha_pll_trion_ops = {

	.prepare = alpha_pll_trion_prepare,

	.enable = clk_trion_pll_enable,