Commit 80c7917d authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-intel-fixes-2021-07-28' of... 

Merge tag 'drm-intel-fixes-2021-07-28' of git://anongit.freedesktop.org/drm/drm-intel

 into drm-fixes

Display related fixes:
- Fix vbt port mask
- Fix around reading the right DSC disable fuse in display_ver 10
- Split display version 9 and 10 in intel_setup_outputs

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YQF63ruuE72x2T45@intel.com
parents 89e7ffd3 b4bde555

drivers/gpu/drm/i915/display/intel_bios.c

+2 −1
Original line number Diff line number Diff line
@@ -2166,7 +2166,8 @@ static void 
init_vbt_missing_defaults(struct drm_i915_private *i915)

{

	enum port port;

	int ports = PORT_A | PORT_B | PORT_C | PORT_D | PORT_E | PORT_F;

	int ports = BIT(PORT_A) | BIT(PORT_B) | BIT(PORT_C) |

		    BIT(PORT_D) | BIT(PORT_E) | BIT(PORT_F);



	if (!HAS_DDI(i915) && !IS_CHERRYVIEW(i915))

		return;

drivers/gpu/drm/i915/display/intel_display.c

+7 −1
Original line number Diff line number Diff line
@@ -11361,13 +11361,19 @@ static void intel_setup_outputs(struct drm_i915_private *dev_priv) 
		intel_ddi_init(dev_priv, PORT_B);

		intel_ddi_init(dev_priv, PORT_C);

		vlv_dsi_init(dev_priv);

	} else if (DISPLAY_VER(dev_priv) >= 9) {

	} else if (DISPLAY_VER(dev_priv) == 10) {

		intel_ddi_init(dev_priv, PORT_A);

		intel_ddi_init(dev_priv, PORT_B);

		intel_ddi_init(dev_priv, PORT_C);

		intel_ddi_init(dev_priv, PORT_D);

		intel_ddi_init(dev_priv, PORT_E);

		intel_ddi_init(dev_priv, PORT_F);

	} else if (DISPLAY_VER(dev_priv) >= 9) {

		intel_ddi_init(dev_priv, PORT_A);

		intel_ddi_init(dev_priv, PORT_B);

		intel_ddi_init(dev_priv, PORT_C);

		intel_ddi_init(dev_priv, PORT_D);

		intel_ddi_init(dev_priv, PORT_E);

	} else if (HAS_DDI(dev_priv)) {

		u32 found;

drivers/gpu/drm/i915/intel_device_info.c

+5 −4
Original line number Diff line number Diff line
@@ -325,7 +325,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 
			info->pipe_mask &= ~BIT(PIPE_C);

			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);

		}

	} else if (HAS_DISPLAY(dev_priv) && GRAPHICS_VER(dev_priv) >= 9) {

	} else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {

		u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);



		if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
@@ -340,7 +340,8 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 
			info->pipe_mask &= ~BIT(PIPE_C);

			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);

		}

		if (GRAPHICS_VER(dev_priv) >= 12 &&



		if (DISPLAY_VER(dev_priv) >= 12 &&

		    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {

			info->pipe_mask &= ~BIT(PIPE_D);

			info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
@@ -352,10 +353,10 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 
		if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)

			info->display.has_fbc = 0;



		if (GRAPHICS_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))

		if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))

			info->display.has_dmc = 0;



		if (GRAPHICS_VER(dev_priv) >= 10 &&

		if (DISPLAY_VER(dev_priv) >= 10 &&

		    (dfsm & CNL_DFSM_DISPLAY_DSC_DISABLE))

			info->display.has_dsc = 0;

	}