Unverified Commit 80c200b3 authored by Conor Dooley's avatar Conor Dooley Committed by Palmer Dabbelt
Browse files

RISC-V: resort all extensions in consistent orders 

Ordering between each and every list of extensions is wildly
inconsistent. Per discussion on the lists pick the following policy:

- The array defining order in /proc/cpuinfo follows a narrow
  interpretation of the ISA specifications, described in a comment
  immediately presiding it.

- All other lists of extensions are sorted alphabetically.

This will hopefully allow for easier review & future additions, and
reduce conflicts between patchsets as the number of extensions grows.

Link: https://lore.kernel.org/all/20221129144742.2935581-2-conor.dooley@microchip.com/


Suggested-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarHeiko Stuebner <heiko.stuebner@vrull.eu>
Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20221205144525.2148448-3-conor.dooley@microchip.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent 99e2266f

arch/riscv/include/asm/hwcap.h

+7 −5
Original line number Diff line number Diff line
@@ -51,14 +51,15 @@ extern unsigned long elf_hwcap; 
 * RISCV_ISA_EXT_MAX. 0-25 range is reserved for single letter

 * extensions while all the multi-letter extensions should define the next

 * available logical extension id.

 * Entries are sorted alphabetically.

 */

enum riscv_isa_ext_id {

	RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE,

	RISCV_ISA_EXT_SSTC,

	RISCV_ISA_EXT_SVINVAL,

	RISCV_ISA_EXT_SVPBMT,

	RISCV_ISA_EXT_ZICBOM,

	RISCV_ISA_EXT_ZIHINTPAUSE,

	RISCV_ISA_EXT_SSTC,

	RISCV_ISA_EXT_SVINVAL,

	RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX,

};
@@ -66,11 +67,12 @@ enum riscv_isa_ext_id { 
 * This enum represents the logical ID for each RISC-V ISA extension static

 * keys. We can use static key to optimize code path if some ISA extensions

 * are available.

 * Entries are sorted alphabetically.

 */

enum riscv_isa_ext_key {

	RISCV_ISA_EXT_KEY_FPU,		/* For 'F' and 'D' */

	RISCV_ISA_EXT_KEY_ZIHINTPAUSE,

	RISCV_ISA_EXT_KEY_SVINVAL,

	RISCV_ISA_EXT_KEY_ZIHINTPAUSE,

	RISCV_ISA_EXT_KEY_MAX,

};
@@ -90,10 +92,10 @@ static __always_inline int riscv_isa_ext2key(int num) 
		return RISCV_ISA_EXT_KEY_FPU;

	case RISCV_ISA_EXT_d:

		return RISCV_ISA_EXT_KEY_FPU;

	case RISCV_ISA_EXT_ZIHINTPAUSE:

		return RISCV_ISA_EXT_KEY_ZIHINTPAUSE;

	case RISCV_ISA_EXT_SVINVAL:

		return RISCV_ISA_EXT_KEY_SVINVAL;

	case RISCV_ISA_EXT_ZIHINTPAUSE:

		return RISCV_ISA_EXT_KEY_ZIHINTPAUSE;

	default:

		return -EINVAL;

	}

arch/riscv/kernel/cpu.c

+2 −2
Original line number Diff line number Diff line
@@ -161,12 +161,12 @@ device_initcall(riscv_cpuinfo_init); 
 * New entries to this struct should follow the ordering rules described above.

 */

static struct riscv_isa_ext_data isa_ext_arr[] = {

	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),

	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),

	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),

	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),

	__RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL),

	__RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT),

	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),

	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),

	__RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX),

};

arch/riscv/kernel/cpufeature.c

+4 −2
Original line number Diff line number Diff line
@@ -199,12 +199,13 @@ void __init riscv_fill_hwcap(void) 
				this_hwcap |= isa2hwcap[(unsigned char)(*ext)];

				set_bit(*ext - 'a', this_isa);

			} else {

				/* sorted alphabetically */

				SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);

				SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);

				SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);

				SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);

				SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);

				SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);

				SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);

				SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);

			}

#undef SET_ISA_EXT_MAP

		}
@@ -284,6 +285,7 @@ static bool __init_or_module cpufeature_probe_zicbom(unsigned int stage) 
 * This code may also be executed before kernel relocation, so we cannot use

 * addresses generated by the address-of operator as they won't be valid in

 * this context.

 * Tests, unless otherwise required, are to be added in alphabetical order.

 */

static u32 __init_or_module cpufeature_probe(unsigned int stage)

{