Commit 8090bea3 authored by Phil Edworthy's avatar Phil Edworthy Committed by Geert Uytterhoeven
Browse files

clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg 



The RZ/V2M doesn't have a matching set of reset monitor regs for each reset
reg like the RZ/G2L. Instead, it has a single CPG_RST_MON reg which has a
single bit per module.

Signed-off-by: default avatarPhil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: default avatarBiju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-10-phil.edworthy@renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 63804400

drivers/clk/renesas/rzg2l-cpg.c

+9 −1
Original line number Diff line number Diff line
@@ -1177,8 +1177,16 @@ static int rzg2l_cpg_status(struct reset_controller_dev *rcdev, 
	const struct rzg2l_cpg_info *info = priv->info;

	unsigned int reg = info->resets[id].off;

	u32 bitmask = BIT(info->resets[id].bit);

	s8 monbit = info->resets[id].monbit;



	if (info->has_clk_mon_regs) {

		return !(readl(priv->base + CLK_MRST_R(reg)) & bitmask);

	} else if (monbit >= 0) {

		u32 monbitmask = BIT(monbit);



		return !!(readl(priv->base + CPG_RST_MON) & monbitmask);

	}

	return -ENOTSUPP;

}



static const struct reset_control_ops rzg2l_cpg_reset_ops = {

drivers/clk/renesas/rzg2l-cpg.h

+8 −2
Original line number Diff line number Diff line
@@ -25,6 +25,7 @@ 
#define CPG_PL6_SSEL		(0x414)

#define CPG_PL6_ETH_SSEL	(0x418)

#define CPG_PL5_SDIV		(0x420)

#define CPG_RST_MON		(0x680)

#define CPG_OTHERFUNC1_REG	(0xBE8)



#define CPG_SIPLL5_STBY_RESETB		BIT(0)
@@ -206,17 +207,22 @@ struct rzg2l_mod_clk { 
 *

 * @off: register offset

 * @bit: reset bit

 * @monbit: monitor bit in CPG_RST_MON register, -1 if none

 */

struct rzg2l_reset {

	u16 off;

	u8 bit;

	s8 monbit;

};



#define DEF_RST(_id, _off, _bit)	\

#define DEF_RST_MON(_id, _off, _bit, _monbit)	\

	[_id] = { \

		.off = (_off), \

		.bit = (_bit) \

		.bit = (_bit), \

		.monbit = (_monbit) \

	}

#define DEF_RST(_id, _off, _bit)	\

	DEF_RST_MON(_id, _off, _bit, -1)



/**

 * struct rzg2l_cpg_info - SoC-specific CPG Description