Commit 8072911b authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'char-misc-5.14-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc 

Pull char/misc fixes from Greg KH:
 "Here are some small char/misc driver fixes for 5.14-rc3.

  Included in here are:

   - MAINTAINERS file updates for two changes in different driver
     subsystems

   - mhi bus bugfixes

   - nds32 bugfix that resolves a reported problem

  All have been in linux-next with no reported problems"

* tag 'char-misc-5.14-rc3' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc:
  nds32: fix up stack guard gap
  MAINTAINERS: Change ACRN HSM driver maintainer
  MAINTAINERS: Update for VMCI driver
  bus: mhi: pci_generic: Fix inbound IPCR channel
  bus: mhi: core: Validate channel ID when processing command completions
  bus: mhi: pci_generic: Apply no-op for wake using sideband wake boolean
parents 74738c55 c453db6c

MAINTAINERS

+9 −1
Original line number Diff line number Diff line
@@ -445,7 +445,7 @@ F: drivers/platform/x86/wmi.c 
F:	include/uapi/linux/wmi.h









ACRN HYPERVISOR SERVICE MODULE









M:	Shuo Liu <shuo.a.liu@intel.com>









M:	Fei Li <fei1.li@intel.com>









L:	acrn-dev@lists.projectacrn.org (subscribers-only)









S:	Supported









W:	https://projectacrn.org








@@ -19801,6 +19801,14 @@ L:	netdev@vger.kernel.org







S:	Supported









F:	drivers/ptp/ptp_vmw.c

















VMWARE VMCI DRIVER









M:	Jorgen Hansen <jhansen@vmware.com>









M:	Vishnu Dasa <vdasa@vmware.com>









L:	linux-kernel@vger.kernel.org









L:	pv-drivers@vmware.com (private)









S:	Maintained









F:	drivers/misc/vmw_vmci/

















VMWARE VMMOUSE SUBDRIVER









M:	"VMware Graphics" <linux-graphics-maintainer@vmware.com>









M:	"VMware, Inc." <pv-drivers@vmware.com>

























arch/nds32/mm/mmap.c



+1
−1






























Original line number
Diff line number
Diff line







@@ -59,7 +59,7 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,

















		vma = find_vma(mm, addr);









		if (TASK_SIZE - len >= addr &&









		    (!vma || addr + len <= vma->vm_start))









		    (!vma || addr + len <= vm_start_gap(vma)))









			return addr;









	}










































drivers/bus/mhi/core/main.c



+12
−5






























Original line number
Diff line number
Diff line







@@ -773,11 +773,18 @@ static void mhi_process_cmd_completion(struct mhi_controller *mhi_cntrl,







	cmd_pkt = mhi_to_virtual(mhi_ring, ptr);



















	chan = MHI_TRE_GET_CMD_CHID(cmd_pkt);



















	if (chan < mhi_cntrl->max_chan &&









	    mhi_cntrl->mhi_chan[chan].configured) {









		mhi_chan = &mhi_cntrl->mhi_chan[chan];









		write_lock_bh(&mhi_chan->lock);









		mhi_chan->ccs = MHI_TRE_GET_EV_CODE(tre);









		complete(&mhi_chan->completion);









		write_unlock_bh(&mhi_chan->lock);









	} else {









		dev_err(&mhi_cntrl->mhi_dev->dev,









			"Completion packet for invalid channel ID: %d\n", chan);









	}



















	mhi_del_ring_element(mhi_cntrl, mhi_ring);









}
































drivers/bus/mhi/pci_generic.c



+36
−9






























Original line number
Diff line number
Diff line







@@ -32,6 +32,8 @@







 * @edl: emergency download mode firmware path (if any)









 * @bar_num: PCI base address register to use for MHI MMIO register space









 * @dma_data_width: DMA transfer word size (32 or 64 bits)









 * @sideband_wake: Devices using dedicated sideband GPIO for wakeup instead









 *		   of inband wake support (such as sdx24)









 */









struct mhi_pci_dev_info {









	const struct mhi_controller_config *config;








@@ -40,6 +42,7 @@ struct mhi_pci_dev_info {







	const char *edl;









	unsigned int bar_num;









	unsigned int dma_data_width;









	bool sideband_wake;









};



















#define MHI_CHANNEL_CONFIG_UL(ch_num, ch_name, el_count, ev_ring) \








@@ -72,6 +75,22 @@ struct mhi_pci_dev_info {







		.doorbell_mode_switch = false,		\









	}



















#define MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(ch_num, ch_name, el_count, ev_ring) \









	{						\









		.num = ch_num,				\









		.name = ch_name,			\









		.num_elements = el_count,		\









		.event_ring = ev_ring,			\









		.dir = DMA_FROM_DEVICE,			\









		.ee_mask = BIT(MHI_EE_AMSS),		\









		.pollcfg = 0,				\









		.doorbell = MHI_DB_BRST_DISABLE,	\









		.lpm_notify = false,			\









		.offload_channel = false,		\









		.doorbell_mode_switch = false,		\









		.auto_queue = true,			\









	}



















#define MHI_EVENT_CONFIG_CTRL(ev_ring, el_count) \









	{					\









		.num_elements = el_count,	\








@@ -210,7 +229,7 @@ static const struct mhi_channel_config modem_qcom_v1_mhi_channels[] = {







	MHI_CHANNEL_CONFIG_UL(14, "QMI", 4, 0),









	MHI_CHANNEL_CONFIG_DL(15, "QMI", 4, 0),









	MHI_CHANNEL_CONFIG_UL(20, "IPCR", 8, 0),









	MHI_CHANNEL_CONFIG_DL(21, "IPCR", 8, 0),









	MHI_CHANNEL_CONFIG_DL_AUTOQUEUE(21, "IPCR", 8, 0),









	MHI_CHANNEL_CONFIG_UL_FP(34, "FIREHOSE", 32, 0),









	MHI_CHANNEL_CONFIG_DL_FP(35, "FIREHOSE", 32, 0),









	MHI_CHANNEL_CONFIG_HW_UL(100, "IP_HW0", 128, 2),








@@ -242,7 +261,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx65_info = {







	.edl = "qcom/sdx65m/edl.mbn",









	.config = &modem_qcom_v1_mhiv_config,









	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,









	.dma_data_width = 32









	.dma_data_width = 32,









	.sideband_wake = false,









};



















static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {








@@ -251,7 +271,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx55_info = {







	.edl = "qcom/sdx55m/edl.mbn",









	.config = &modem_qcom_v1_mhiv_config,









	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,









	.dma_data_width = 32









	.dma_data_width = 32,









	.sideband_wake = false,









};



















static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = {








@@ -259,7 +280,8 @@ static const struct mhi_pci_dev_info mhi_qcom_sdx24_info = {







	.edl = "qcom/prog_firehose_sdx24.mbn",









	.config = &modem_qcom_v1_mhiv_config,









	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,









	.dma_data_width = 32









	.dma_data_width = 32,









	.sideband_wake = true,









};



















static const struct mhi_channel_config mhi_quectel_em1xx_channels[] = {








@@ -301,7 +323,8 @@ static const struct mhi_pci_dev_info mhi_quectel_em1xx_info = {







	.edl = "qcom/prog_firehose_sdx24.mbn",









	.config = &modem_quectel_em1xx_config,









	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,









	.dma_data_width = 32









	.dma_data_width = 32,









	.sideband_wake = true,









};



















static const struct mhi_channel_config mhi_foxconn_sdx55_channels[] = {








@@ -339,7 +362,8 @@ static const struct mhi_pci_dev_info mhi_foxconn_sdx55_info = {







	.edl = "qcom/sdx55m/edl.mbn",









	.config = &modem_foxconn_sdx55_config,









	.bar_num = MHI_PCI_DEFAULT_BAR_NUM,









	.dma_data_width = 32









	.dma_data_width = 32,









	.sideband_wake = false,









};



















static const struct pci_device_id mhi_pci_id_table[] = {








@@ -640,9 +664,12 @@ static int mhi_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)







	mhi_cntrl->status_cb = mhi_pci_status_cb;









	mhi_cntrl->runtime_get = mhi_pci_runtime_get;









	mhi_cntrl->runtime_put = mhi_pci_runtime_put;



















	if (info->sideband_wake) {









		mhi_cntrl->wake_get = mhi_pci_wake_get_nop;









		mhi_cntrl->wake_put = mhi_pci_wake_put_nop;









		mhi_cntrl->wake_toggle = mhi_pci_wake_toggle_nop;









	}



















	err = mhi_pci_claim(mhi_cntrl, info->bar_num, DMA_BIT_MASK(info->dma_data_width));









	if (err)