Commit 806521bc authored by Martin Habets's avatar Martin Habets Committed by David S. Miller
Browse files

sfc: Remove falcon references 



Siena was using functions from the Falcon architecture.
These start with the efx_farch prefix.
Now that both of these are in separate modules the references
are no longer used in the sfc.ko module.

Signed-off-by: default avatarMartin Habets <habetsm.xilinx@gmail.com>
Acked-by: default avatarEdward Cree <ecree.xilinx@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent be923772

drivers/net/ethernet/sfc/farch_regs.h

deleted100644 → 0
+0 −2929

File deleted.

Preview size limit exceeded, changes collapsed.

drivers/net/ethernet/sfc/mcdi.c

+0 −1
Original line number Diff line number Diff line
@@ -10,7 +10,6 @@ 
#include "net_driver.h"

#include "nic.h"

#include "io.h"

#include "farch_regs.h"

#include "mcdi_pcol.h"



/**************************************************************************

drivers/net/ethernet/sfc/net_driver.h

+2 −3
Original line number Diff line number Diff line
@@ -237,7 +237,7 @@ struct efx_tx_buffer { 
 *	Normally this will equal @write_count, but as option descriptors

 *	don't produce completion events, they won't update this.

 *	Filled in iff @efx->type->option_descriptors; only used for PIO.

 *	Thus, this is written and used on EF10, and neither on farch.

 *	Thus, this is only written and used on EF10.

 * @old_read_count: The value of read_count when last checked.

 *	This is here for performance reasons.  The xmit path will

 *	only get the up-to-date value of read_count if this
@@ -1288,8 +1288,7 @@ struct efx_udp_tunnel { 
 * @set_wol: Push WoL configuration to the NIC

 * @resume_wol: Synchronise WoL state between driver and MC (e.g. after resume)

 * @get_fec_stats: Get standard FEC statistics.

 * @test_chip: Test registers.  May use efx_farch_test_registers(), and is

 *	expected to reset the NIC.

 * @test_chip: Test registers. This is expected to reset the NIC.

 * @test_nvram: Test validity of NVRAM contents

 * @mcdi_request: Send an MCDI request with the given header and SDU.

 *	The SDU length may be any value from 0 up to the protocol-

drivers/net/ethernet/sfc/nic.c

+0 −153
Original line number Diff line number Diff line
@@ -17,7 +17,6 @@ 
#include "efx.h"

#include "nic.h"

#include "ef10_regs.h"

#include "farch_regs.h"

#include "io.h"

#include "workarounds.h"

#include "mcdi_pcol.h"
@@ -172,10 +171,6 @@ void efx_nic_fini_interrupt(struct efx_nic *efx) 


/* Register dump */



#define REGISTER_REVISION_FA	1

#define REGISTER_REVISION_FB	2

#define REGISTER_REVISION_FC	3

#define REGISTER_REVISION_FZ	3	/* last Falcon arch revision */

#define REGISTER_REVISION_ED	4

#define REGISTER_REVISION_EZ	4	/* latest EF10 revision */
@@ -189,117 +184,9 @@ struct efx_nic_reg { 
	REGISTER_REVISION_ ## arch ## min_rev,				\

	REGISTER_REVISION_ ## arch ## max_rev				\

}

#define REGISTER_AA(name) REGISTER(name, F, A, A)

#define REGISTER_AB(name) REGISTER(name, F, A, B)

#define REGISTER_AZ(name) REGISTER(name, F, A, Z)

#define REGISTER_BB(name) REGISTER(name, F, B, B)

#define REGISTER_BZ(name) REGISTER(name, F, B, Z)

#define REGISTER_CZ(name) REGISTER(name, F, C, Z)

#define REGISTER_DZ(name) REGISTER(name, E, D, Z)



static const struct efx_nic_reg efx_nic_regs[] = {

	REGISTER_AZ(ADR_REGION),

	REGISTER_AZ(INT_EN_KER),

	REGISTER_BZ(INT_EN_CHAR),

	REGISTER_AZ(INT_ADR_KER),

	REGISTER_BZ(INT_ADR_CHAR),

	/* INT_ACK_KER is WO */

	/* INT_ISR0 is RC */

	REGISTER_AZ(HW_INIT),

	REGISTER_CZ(USR_EV_CFG),

	REGISTER_AB(EE_SPI_HCMD),

	REGISTER_AB(EE_SPI_HADR),

	REGISTER_AB(EE_SPI_HDATA),

	REGISTER_AB(EE_BASE_PAGE),

	REGISTER_AB(EE_VPD_CFG0),

	/* EE_VPD_SW_CNTL and EE_VPD_SW_DATA are not used */

	/* PMBX_DBG_IADDR and PBMX_DBG_IDATA are indirect */

	/* PCIE_CORE_INDIRECT is indirect */

	REGISTER_AB(NIC_STAT),

	REGISTER_AB(GPIO_CTL),

	REGISTER_AB(GLB_CTL),

	/* FATAL_INTR_KER and FATAL_INTR_CHAR are partly RC */

	REGISTER_BZ(DP_CTRL),

	REGISTER_AZ(MEM_STAT),

	REGISTER_AZ(CS_DEBUG),

	REGISTER_AZ(ALTERA_BUILD),

	REGISTER_AZ(CSR_SPARE),

	REGISTER_AB(PCIE_SD_CTL0123),

	REGISTER_AB(PCIE_SD_CTL45),

	REGISTER_AB(PCIE_PCS_CTL_STAT),

	/* DEBUG_DATA_OUT is not used */

	/* DRV_EV is WO */

	REGISTER_AZ(EVQ_CTL),

	REGISTER_AZ(EVQ_CNT1),

	REGISTER_AZ(EVQ_CNT2),

	REGISTER_AZ(BUF_TBL_CFG),

	REGISTER_AZ(SRM_RX_DC_CFG),

	REGISTER_AZ(SRM_TX_DC_CFG),

	REGISTER_AZ(SRM_CFG),

	/* BUF_TBL_UPD is WO */

	REGISTER_AZ(SRM_UPD_EVQ),

	REGISTER_AZ(SRAM_PARITY),

	REGISTER_AZ(RX_CFG),

	REGISTER_BZ(RX_FILTER_CTL),

	/* RX_FLUSH_DESCQ is WO */

	REGISTER_AZ(RX_DC_CFG),

	REGISTER_AZ(RX_DC_PF_WM),

	REGISTER_BZ(RX_RSS_TKEY),

	/* RX_NODESC_DROP is RC */

	REGISTER_AA(RX_SELF_RST),

	/* RX_DEBUG, RX_PUSH_DROP are not used */

	REGISTER_CZ(RX_RSS_IPV6_REG1),

	REGISTER_CZ(RX_RSS_IPV6_REG2),

	REGISTER_CZ(RX_RSS_IPV6_REG3),

	/* TX_FLUSH_DESCQ is WO */

	REGISTER_AZ(TX_DC_CFG),

	REGISTER_AA(TX_CHKSM_CFG),

	REGISTER_AZ(TX_CFG),

	/* TX_PUSH_DROP is not used */

	REGISTER_AZ(TX_RESERVED),

	REGISTER_BZ(TX_PACE),

	/* TX_PACE_DROP_QID is RC */

	REGISTER_BB(TX_VLAN),

	REGISTER_BZ(TX_IPFIL_PORTEN),

	REGISTER_AB(MD_TXD),

	REGISTER_AB(MD_RXD),

	REGISTER_AB(MD_CS),

	REGISTER_AB(MD_PHY_ADR),

	REGISTER_AB(MD_ID),

	/* MD_STAT is RC */

	REGISTER_AB(MAC_STAT_DMA),

	REGISTER_AB(MAC_CTRL),

	REGISTER_BB(GEN_MODE),

	REGISTER_AB(MAC_MC_HASH_REG0),

	REGISTER_AB(MAC_MC_HASH_REG1),

	REGISTER_AB(GM_CFG1),

	REGISTER_AB(GM_CFG2),

	/* GM_IPG and GM_HD are not used */

	REGISTER_AB(GM_MAX_FLEN),

	/* GM_TEST is not used */

	REGISTER_AB(GM_ADR1),

	REGISTER_AB(GM_ADR2),

	REGISTER_AB(GMF_CFG0),

	REGISTER_AB(GMF_CFG1),

	REGISTER_AB(GMF_CFG2),

	REGISTER_AB(GMF_CFG3),

	REGISTER_AB(GMF_CFG4),

	REGISTER_AB(GMF_CFG5),

	REGISTER_BB(TX_SRC_MAC_CTL),

	REGISTER_AB(XM_ADR_LO),

	REGISTER_AB(XM_ADR_HI),

	REGISTER_AB(XM_GLB_CFG),

	REGISTER_AB(XM_TX_CFG),

	REGISTER_AB(XM_RX_CFG),

	REGISTER_AB(XM_MGT_INT_MASK),

	REGISTER_AB(XM_FC),

	REGISTER_AB(XM_PAUSE_TIME),

	REGISTER_AB(XM_TX_PARAM),

	REGISTER_AB(XM_RX_PARAM),

	/* XM_MGT_INT_MSK (note no 'A') is RC */

	REGISTER_AB(XX_PWR_RST),

	REGISTER_AB(XX_SD_CTL),

	REGISTER_AB(XX_TXDRV_CTL),

	/* XX_PRBS_CTL, XX_PRBS_CHK and XX_PRBS_ERR are not used */

	/* XX_CORE_STAT is partly RC */

	REGISTER_DZ(BIU_HW_REV_ID),
@@ -325,49 +212,9 @@ struct efx_nic_reg_table { 
		arch, min_rev, max_rev,					\

		arch ## R_ ## min_rev ## max_rev ## _ ## name ## _STEP,	\

		arch ## R_ ## min_rev ## max_rev ## _ ## name ## _ROWS)

#define REGISTER_TABLE_AA(name) REGISTER_TABLE(name, F, A, A)

#define REGISTER_TABLE_AZ(name) REGISTER_TABLE(name, F, A, Z)

#define REGISTER_TABLE_BB(name) REGISTER_TABLE(name, F, B, B)

#define REGISTER_TABLE_BZ(name) REGISTER_TABLE(name, F, B, Z)

#define REGISTER_TABLE_BB_CZ(name)					\

	REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, B, B,	\

				  FR_BZ_ ## name ## _STEP,		\

				  FR_BB_ ## name ## _ROWS),		\

	REGISTER_TABLE_DIMENSIONS(name, FR_BZ_ ## name, F, C, Z,	\

				  FR_BZ_ ## name ## _STEP,		\

				  FR_CZ_ ## name ## _ROWS)

#define REGISTER_TABLE_CZ(name) REGISTER_TABLE(name, F, C, Z)

#define REGISTER_TABLE_DZ(name) REGISTER_TABLE(name, E, D, Z)



static const struct efx_nic_reg_table efx_nic_reg_tables[] = {

	/* DRIVER is not used */

	/* EVQ_RPTR, TIMER_COMMAND, USR_EV and {RX,TX}_DESC_UPD are WO */

	REGISTER_TABLE_BB(TX_IPFIL_TBL),

	REGISTER_TABLE_BB(TX_SRC_MAC_TBL),

	REGISTER_TABLE_AA(RX_DESC_PTR_TBL_KER),

	REGISTER_TABLE_BB_CZ(RX_DESC_PTR_TBL),

	REGISTER_TABLE_AA(TX_DESC_PTR_TBL_KER),

	REGISTER_TABLE_BB_CZ(TX_DESC_PTR_TBL),

	REGISTER_TABLE_AA(EVQ_PTR_TBL_KER),

	REGISTER_TABLE_BB_CZ(EVQ_PTR_TBL),

	/* We can't reasonably read all of the buffer table (up to 8MB!).

	 * However this driver will only use a few entries.  Reading

	 * 1K entries allows for some expansion of queue count and

	 * size before we need to change the version. */

	REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL_KER, FR_AA_BUF_FULL_TBL_KER,

				  F, A, A, 8, 1024),

	REGISTER_TABLE_DIMENSIONS(BUF_FULL_TBL, FR_BZ_BUF_FULL_TBL,

				  F, B, Z, 8, 1024),

	REGISTER_TABLE_CZ(RX_MAC_FILTER_TBL0),

	REGISTER_TABLE_BB_CZ(TIMER_TBL),

	REGISTER_TABLE_BB_CZ(TX_PACE_TBL),

	REGISTER_TABLE_BZ(RX_INDIRECTION_TBL),

	/* TX_FILTER_TBL0 is huge and not used by this driver */

	REGISTER_TABLE_CZ(TX_MAC_FILTER_TBL0),

	REGISTER_TABLE_CZ(MC_TREG_SMEM),

	/* MSIX_PBA_TABLE is not mapped */

	/* SRM_DBG is not mapped (and is redundant with BUF_FLL_TBL) */

	REGISTER_TABLE_BZ(RX_FILTER_TBL0),

	REGISTER_TABLE_DZ(BIU_MC_SFT_STATUS),

};

drivers/net/ethernet/sfc/nic.h

+0 −83
Original line number Diff line number Diff line
@@ -11,8 +11,6 @@ 
#include "nic_common.h"

#include "efx.h"



u32 efx_farch_fpga_ver(struct efx_nic *efx);



enum {

	PHY_TYPE_NONE = 0,

	PHY_TYPE_TXC43128 = 1,
@@ -304,89 +302,8 @@ int efx_ef10_tx_tso_desc(struct efx_tx_queue *tx_queue, struct sk_buff *skb, 
extern const struct efx_nic_type efx_hunt_a0_nic_type;

extern const struct efx_nic_type efx_hunt_a0_vf_nic_type;



int falcon_probe_board(struct efx_nic *efx, u16 revision_info);



/* Falcon/Siena queue operations */

int efx_farch_tx_probe(struct efx_tx_queue *tx_queue);

void efx_farch_tx_init(struct efx_tx_queue *tx_queue);

void efx_farch_tx_fini(struct efx_tx_queue *tx_queue);

void efx_farch_tx_remove(struct efx_tx_queue *tx_queue);

void efx_farch_tx_write(struct efx_tx_queue *tx_queue);

unsigned int efx_farch_tx_limit_len(struct efx_tx_queue *tx_queue,

				    dma_addr_t dma_addr, unsigned int len);

int efx_farch_rx_probe(struct efx_rx_queue *rx_queue);

void efx_farch_rx_init(struct efx_rx_queue *rx_queue);

void efx_farch_rx_fini(struct efx_rx_queue *rx_queue);

void efx_farch_rx_remove(struct efx_rx_queue *rx_queue);

void efx_farch_rx_write(struct efx_rx_queue *rx_queue);

void efx_farch_rx_defer_refill(struct efx_rx_queue *rx_queue);

int efx_farch_ev_probe(struct efx_channel *channel);

int efx_farch_ev_init(struct efx_channel *channel);

void efx_farch_ev_fini(struct efx_channel *channel);

void efx_farch_ev_remove(struct efx_channel *channel);

int efx_farch_ev_process(struct efx_channel *channel, int quota);

void efx_farch_ev_read_ack(struct efx_channel *channel);

void efx_farch_ev_test_generate(struct efx_channel *channel);



/* Falcon/Siena filter operations */

int efx_farch_filter_table_probe(struct efx_nic *efx);

void efx_farch_filter_table_restore(struct efx_nic *efx);

void efx_farch_filter_table_remove(struct efx_nic *efx);

void efx_farch_filter_update_rx_scatter(struct efx_nic *efx);

s32 efx_farch_filter_insert(struct efx_nic *efx, struct efx_filter_spec *spec,

			    bool replace);

int efx_farch_filter_remove_safe(struct efx_nic *efx,

				 enum efx_filter_priority priority,

				 u32 filter_id);

int efx_farch_filter_get_safe(struct efx_nic *efx,

			      enum efx_filter_priority priority, u32 filter_id,

			      struct efx_filter_spec *);

int efx_farch_filter_clear_rx(struct efx_nic *efx,

			      enum efx_filter_priority priority);

u32 efx_farch_filter_count_rx_used(struct efx_nic *efx,

				   enum efx_filter_priority priority);

u32 efx_farch_filter_get_rx_id_limit(struct efx_nic *efx);

s32 efx_farch_filter_get_rx_ids(struct efx_nic *efx,

				enum efx_filter_priority priority, u32 *buf,

				u32 size);

#ifdef CONFIG_RFS_ACCEL

bool efx_farch_filter_rfs_expire_one(struct efx_nic *efx, u32 flow_id,

				     unsigned int index);

#endif

void efx_farch_filter_sync_rx_mode(struct efx_nic *efx);



/* Falcon/Siena interrupts */

void efx_farch_irq_enable_master(struct efx_nic *efx);

int efx_farch_irq_test_generate(struct efx_nic *efx);

void efx_farch_irq_disable_master(struct efx_nic *efx);

irqreturn_t efx_farch_msi_interrupt(int irq, void *dev_id);

irqreturn_t efx_farch_legacy_interrupt(int irq, void *dev_id);

irqreturn_t efx_farch_fatal_interrupt(struct efx_nic *efx);



/* Global Resources */

void siena_prepare_flush(struct efx_nic *efx);

int efx_farch_fini_dmaq(struct efx_nic *efx);

void efx_farch_finish_flr(struct efx_nic *efx);

void siena_finish_flush(struct efx_nic *efx);

void falcon_start_nic_stats(struct efx_nic *efx);

void falcon_stop_nic_stats(struct efx_nic *efx);

int falcon_reset_xaui(struct efx_nic *efx);

void efx_farch_dimension_resources(struct efx_nic *efx, unsigned sram_lim_qw);

void efx_farch_init_common(struct efx_nic *efx);

void efx_farch_rx_push_indir_table(struct efx_nic *efx);

void efx_farch_rx_pull_indir_table(struct efx_nic *efx);



/* Tests */

struct efx_farch_register_test {

	unsigned address;

	efx_oword_t mask;

};



int efx_farch_test_registers(struct efx_nic *efx,

			     const struct efx_farch_register_test *regs,

			     size_t n_regs);



void efx_farch_generate_event(struct efx_nic *efx, unsigned int evq,

			      efx_qword_t *event);



#endif /* EFX_NIC_H */