Commit 8024edf3 authored by David S. Miller's avatar David S. Miller
Browse files

Merge branch 'net-ipa-GSI-regs' 



Alex Elder says:

====================
net: ipa: determine GSI register offsets differently

This series changes the way GSI register offset are specified, using
the "reg" mechanism currently used for IPA registers.  A follow-on
series will extend this work so fields within GSI registers are also
specified this way.

The first patch rearranges the GSI register initialization code so
it is similar to the way it's done for the IPA registers.  The
second identifies all the GSI registers in an enumerated type.
The third introduces "gsi_reg-v3.1.c" and uses the "reg" code to
define one GSI register offset.  The second-to-last patch just
adds "gsi_reg-v3.5.1.c", because that version introduces a new
register not previously defined.  All the rest just define the
rest of the GSI register offsets using the "reg" mechanism.

Note that, to have continued lines align with an open parenthesis,
new files created in this series cause some checkpatch warnings.
====================

Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 4fab6412 5791a73c

drivers/net/ipa/Makefile

+7 −2
Original line number Diff line number Diff line
@@ -4,15 +4,20 @@ 


IPA_VERSIONS		:=	3.1 3.5.1 4.2 4.5 4.7 4.9 4.11



# Some IPA versions can reuse another set of GSI register definitions.

GSI_IPA_VERSIONS	:=	3.1 3.5.1



obj-$(CONFIG_QCOM_IPA)	+=	ipa.o



ipa-y			:=	ipa_main.o ipa_power.o ipa_reg.o ipa_mem.o \

				ipa_table.o ipa_interrupt.o gsi.o gsi_trans.o \

				ipa_gsi.o ipa_smp2p.o ipa_uc.o \

				ipa_table.o ipa_interrupt.o gsi.o gsi_reg.o \

				gsi_trans.o ipa_gsi.o ipa_smp2p.o ipa_uc.o \

				ipa_endpoint.o ipa_cmd.o ipa_modem.o \

				ipa_resource.o ipa_qmi.o ipa_qmi_msg.o \

				ipa_sysfs.o



ipa-y			+=	$(GSI_IPA_VERSIONS:%=reg/gsi_reg-v%.o)



ipa-y			+=	$(IPA_VERSIONS:%=reg/ipa_reg-v%.o)



ipa-y			+=	$(IPA_VERSIONS:%=data/ipa_data-v%.o)

drivers/net/ipa/gsi.c

+223 −117

File changed.

Preview size limit exceeded, changes collapsed.

drivers/net/ipa/gsi.h

+3 −1
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */



/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

 * Copyright (C) 2018-2022 Linaro Ltd.

 * Copyright (C) 2018-2023 Linaro Ltd.

 */

#ifndef _GSI_H_

#define _GSI_H_
@@ -142,6 +142,8 @@ struct gsi { 
	enum ipa_version version;

	void __iomem *virt_raw;		/* I/O mapped address range */

	void __iomem *virt;		/* Adjusted for most registers */

	const struct regs *regs;



	u32 irq;

	u32 channel_count;

	u32 evt_ring_count;

drivers/net/ipa/gsi_reg.c

0 → 100644
+168 −0
Original line number Diff line number Diff line 
// SPDX-License-Identifier: GPL-2.0



/* Copyright (C) 2023 Linaro Ltd. */



#include <linux/platform_device.h>

#include <linux/io.h>



#include "gsi.h"

#include "reg.h"

#include "gsi_reg.h"



/* GSI EE registers as a group are shifted downward by a fixed constant amount

 * for IPA versions 4.5 and beyond.  This applies to all GSI registers we use

 * *except* the ones that disable inter-EE interrupts for channels and event

 * channels.

 *

 * The "raw" (not adjusted) GSI register range is mapped, and a pointer to

 * the mapped range is held in gsi->virt_raw.  The inter-EE interrupt

 * registers are accessed using that pointer.

 *

 * Most registers are accessed using gsi->virt, which is a copy of the "raw"

 * pointer, adjusted downward by the fixed amount.

 */

#define GSI_EE_REG_ADJUST	0x0000d000			/* IPA v4.5+ */



/* Is this register ID valid for the current GSI version? */

static bool gsi_reg_id_valid(struct gsi *gsi, enum gsi_reg_id reg_id)

{

	switch (reg_id) {

	case INTER_EE_SRC_CH_IRQ_MSK:

	case INTER_EE_SRC_EV_CH_IRQ_MSK:

	case CH_C_CNTXT_0:

	case CH_C_CNTXT_1:

	case CH_C_CNTXT_2:

	case CH_C_CNTXT_3:

	case CH_C_QOS:

	case CH_C_SCRATCH_0:

	case CH_C_SCRATCH_1:

	case CH_C_SCRATCH_2:

	case CH_C_SCRATCH_3:

	case EV_CH_E_CNTXT_0:

	case EV_CH_E_CNTXT_1:

	case EV_CH_E_CNTXT_2:

	case EV_CH_E_CNTXT_3:

	case EV_CH_E_CNTXT_4:

	case EV_CH_E_CNTXT_8:

	case EV_CH_E_CNTXT_9:

	case EV_CH_E_CNTXT_10:

	case EV_CH_E_CNTXT_11:

	case EV_CH_E_CNTXT_12:

	case EV_CH_E_CNTXT_13:

	case EV_CH_E_SCRATCH_0:

	case EV_CH_E_SCRATCH_1:

	case CH_C_DOORBELL_0:

	case EV_CH_E_DOORBELL_0:

	case GSI_STATUS:

	case CH_CMD:

	case EV_CH_CMD:

	case GENERIC_CMD:

	case HW_PARAM_2:

	case CNTXT_TYPE_IRQ:

	case CNTXT_TYPE_IRQ_MSK:

	case CNTXT_SRC_CH_IRQ:

	case CNTXT_SRC_CH_IRQ_MSK:

	case CNTXT_SRC_CH_IRQ_CLR:

	case CNTXT_SRC_EV_CH_IRQ:

	case CNTXT_SRC_EV_CH_IRQ_MSK:

	case CNTXT_SRC_EV_CH_IRQ_CLR:

	case CNTXT_SRC_IEOB_IRQ:

	case CNTXT_SRC_IEOB_IRQ_MSK:

	case CNTXT_SRC_IEOB_IRQ_CLR:

	case CNTXT_GLOB_IRQ_STTS:

	case CNTXT_GLOB_IRQ_EN:

	case CNTXT_GLOB_IRQ_CLR:

	case CNTXT_GSI_IRQ_STTS:

	case CNTXT_GSI_IRQ_EN:

	case CNTXT_GSI_IRQ_CLR:

	case CNTXT_INTSET:

	case ERROR_LOG:

	case ERROR_LOG_CLR:

	case CNTXT_SCRATCH_0:

		return true;



	default:

		return false;

	}

}



const struct reg *gsi_reg(struct gsi *gsi, enum gsi_reg_id reg_id)

{

	if (WARN(!gsi_reg_id_valid(gsi, reg_id), "invalid reg %u\n", reg_id))

		return NULL;



	return reg(gsi->regs, reg_id);

}



static const struct regs *gsi_regs(struct gsi *gsi)

{

	switch (gsi->version) {

	case IPA_VERSION_3_1:

		return &gsi_regs_v3_1;



	case IPA_VERSION_3_5_1:

	case IPA_VERSION_4_2:

	case IPA_VERSION_4_5:

	case IPA_VERSION_4_7:

	case IPA_VERSION_4_9:

	case IPA_VERSION_4_11:

		return &gsi_regs_v3_5_1;



	default:

		return NULL;

	}

}



/* Sets gsi->virt_raw and gsi->virt, and I/O maps the "gsi" memory range */

int gsi_reg_init(struct gsi *gsi, struct platform_device *pdev)

{

	struct device *dev = &pdev->dev;

	struct resource *res;

	resource_size_t size;

	u32 adjust;



	/* Get GSI memory range and map it */

	res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gsi");

	if (!res) {

		dev_err(dev, "DT error getting \"gsi\" memory property\n");

		return -ENODEV;

	}



	size = resource_size(res);

	if (res->start > U32_MAX || size > U32_MAX - res->start) {

		dev_err(dev, "DT memory resource \"gsi\" out of range\n");

		return -EINVAL;

	}



	/* Make sure we can make our pointer adjustment if necessary */

	adjust = gsi->version < IPA_VERSION_4_5 ? 0 : GSI_EE_REG_ADJUST;

	if (res->start < adjust) {

		dev_err(dev, "DT memory resource \"gsi\" too low (< %u)\n",

			adjust);

		return -EINVAL;

	}



	gsi->regs = gsi_regs(gsi);

	if (!gsi->regs) {

		dev_err(dev, "unsupported IPA version %u (?)\n", gsi->version);

		return -EINVAL;

	}



	gsi->virt_raw = ioremap(res->start, size);

	if (!gsi->virt_raw) {

		dev_err(dev, "unable to remap \"gsi\" memory\n");

		return -ENOMEM;

	}

	/* Most registers are accessed using an adjusted register range */

	gsi->virt = gsi->virt_raw - adjust;



	return 0;

}



/* Inverse of gsi_reg_init() */

void gsi_reg_exit(struct gsi *gsi)

{

	gsi->virt = NULL;

	iounmap(gsi->virt_raw);

	gsi->virt_raw = NULL;

}

drivers/net/ipa/gsi_reg.h

+97 −161
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0 */



/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

 * Copyright (C) 2018-2022 Linaro Ltd.

 * Copyright (C) 2018-2023 Linaro Ltd.

 */

#ifndef _GSI_REG_H_

#define _GSI_REG_H_



/* === Only "gsi.c" should include this file === */

/* === Only "gsi.c" and "gsi_reg.c" should include this file === */



#include <linux/bits.h>
@@ -38,32 +38,64 @@ 
 * (though the actual limit is hardware-dependent).

 */



/* GSI EE registers as a group are shifted downward by a fixed constant amount

 * for IPA versions 4.5 and beyond.  This applies to all GSI registers we use

 * *except* the ones that disable inter-EE interrupts for channels and event

 * channels.

 *

 * The "raw" (not adjusted) GSI register range is mapped, and a pointer to

 * the mapped range is held in gsi->virt_raw.  The inter-EE interrupt

 * registers are accessed using that pointer.

 *

 * Most registers are accessed using gsi->virt, which is a copy of the "raw"

 * pointer, adjusted downward by the fixed amount.

 */

#define GSI_EE_REG_ADJUST			0x0000d000	/* IPA v4.5+ */



/* The inter-EE IRQ registers are relative to gsi->virt_raw (IPA v3.5+) */



#define GSI_INTER_EE_SRC_CH_IRQ_MSK_OFFSET \

			(0x0000c020 + 0x1000 * GSI_EE_AP)



#define GSI_INTER_EE_SRC_EV_CH_IRQ_MSK_OFFSET \

			(0x0000c024 + 0x1000 * GSI_EE_AP)



/* All other register offsets are relative to gsi->virt */

/* enum gsi_reg_id - GSI register IDs */

enum gsi_reg_id {

	INTER_EE_SRC_CH_IRQ_MSK,			/* IPA v3.5+ */

	INTER_EE_SRC_EV_CH_IRQ_MSK,			/* IPA v3.5+ */

	CH_C_CNTXT_0,

	CH_C_CNTXT_1,

	CH_C_CNTXT_2,

	CH_C_CNTXT_3,

	CH_C_QOS,

	CH_C_SCRATCH_0,

	CH_C_SCRATCH_1,

	CH_C_SCRATCH_2,

	CH_C_SCRATCH_3,

	EV_CH_E_CNTXT_0,

	EV_CH_E_CNTXT_1,

	EV_CH_E_CNTXT_2,

	EV_CH_E_CNTXT_3,

	EV_CH_E_CNTXT_4,

	EV_CH_E_CNTXT_8,

	EV_CH_E_CNTXT_9,

	EV_CH_E_CNTXT_10,

	EV_CH_E_CNTXT_11,

	EV_CH_E_CNTXT_12,

	EV_CH_E_CNTXT_13,

	EV_CH_E_SCRATCH_0,

	EV_CH_E_SCRATCH_1,

	CH_C_DOORBELL_0,

	EV_CH_E_DOORBELL_0,

	GSI_STATUS,

	CH_CMD,

	EV_CH_CMD,

	GENERIC_CMD,

	HW_PARAM_2,					/* IPA v3.5.1+ */

	CNTXT_TYPE_IRQ,

	CNTXT_TYPE_IRQ_MSK,

	CNTXT_SRC_CH_IRQ,

	CNTXT_SRC_CH_IRQ_MSK,

	CNTXT_SRC_CH_IRQ_CLR,

	CNTXT_SRC_EV_CH_IRQ,

	CNTXT_SRC_EV_CH_IRQ_MSK,

	CNTXT_SRC_EV_CH_IRQ_CLR,

	CNTXT_SRC_IEOB_IRQ,

	CNTXT_SRC_IEOB_IRQ_MSK,

	CNTXT_SRC_IEOB_IRQ_CLR,

	CNTXT_GLOB_IRQ_STTS,

	CNTXT_GLOB_IRQ_EN,

	CNTXT_GLOB_IRQ_CLR,

	CNTXT_GSI_IRQ_STTS,

	CNTXT_GSI_IRQ_EN,

	CNTXT_GSI_IRQ_CLR,

	CNTXT_INTSET,

	ERROR_LOG,

	ERROR_LOG_CLR,

	CNTXT_SCRATCH_0,

	GSI_REG_ID_COUNT,				/* Last; not an ID */

};



#define GSI_CH_C_CNTXT_0_OFFSET(ch) \

			(0x0001c000 + 0x4000 * GSI_EE_AP + 0x80 * (ch))

/* CH_C_CNTXT_0 register */

#define CHTYPE_PROTOCOL_FMASK		GENMASK(2, 0)

#define CHTYPE_DIR_FMASK		GENMASK(3, 3)

#define EE_FMASK			GENMASK(7, 4)
@@ -88,17 +120,7 @@ enum gsi_channel_type { 
	GSI_CHANNEL_TYPE_11AD			= 0x9,

};



#define GSI_CH_C_CNTXT_1_OFFSET(ch) \

			(0x0001c004 + 0x4000 * GSI_EE_AP + 0x80 * (ch))



#define GSI_CH_C_CNTXT_2_OFFSET(ch) \

			(0x0001c008 + 0x4000 * GSI_EE_AP + 0x80 * (ch))



#define GSI_CH_C_CNTXT_3_OFFSET(ch) \

			(0x0001c00c + 0x4000 * GSI_EE_AP + 0x80 * (ch))



#define GSI_CH_C_QOS_OFFSET(ch) \

			(0x0001c05c + 0x4000 * GSI_EE_AP + 0x80 * (ch))

/* CH_C_QOS register */

#define WRR_WEIGHT_FMASK		GENMASK(3, 0)

#define MAX_PREFETCH_FMASK		GENMASK(8, 8)

#define USE_DB_ENG_FMASK		GENMASK(9, 9)
@@ -118,20 +140,7 @@ enum gsi_prefetch_mode { 
	GSI_FREE_PREFETCH			= 0x3,

};



#define GSI_CH_C_SCRATCH_0_OFFSET(ch) \

			(0x0001c060 + 0x4000 * GSI_EE_AP + 0x80 * (ch))



#define GSI_CH_C_SCRATCH_1_OFFSET(ch) \

			(0x0001c064 + 0x4000 * GSI_EE_AP + 0x80 * (ch))



#define GSI_CH_C_SCRATCH_2_OFFSET(ch) \

			(0x0001c068 + 0x4000 * GSI_EE_AP + 0x80 * (ch))



#define GSI_CH_C_SCRATCH_3_OFFSET(ch) \

			(0x0001c06c + 0x4000 * GSI_EE_AP + 0x80 * (ch))



#define GSI_EV_CH_E_CNTXT_0_OFFSET(ev) \

			(0x0001d000 + 0x4000 * GSI_EE_AP + 0x80 * (ev))

/* EV_CH_E_CNTXT_0 register */

/* enum gsi_channel_type defines EV_CHTYPE field values in EV_CH_E_CNTXT_0 */

#define EV_CHTYPE_FMASK			GENMASK(3, 0)

#define EV_EE_FMASK			GENMASK(7, 4)
@@ -140,57 +149,15 @@ enum gsi_prefetch_mode { 
#define EV_CHSTATE_FMASK		GENMASK(23, 20)

#define EV_ELEMENT_SIZE_FMASK		GENMASK(31, 24)



#define GSI_EV_CH_E_CNTXT_1_OFFSET(ev) \

			(0x0001d004 + 0x4000 * GSI_EE_AP + 0x80 * (ev))



#define GSI_EV_CH_E_CNTXT_2_OFFSET(ev) \

			(0x0001d008 + 0x4000 * GSI_EE_AP + 0x80 * (ev))



#define GSI_EV_CH_E_CNTXT_3_OFFSET(ev) \

			(0x0001d00c + 0x4000 * GSI_EE_AP + 0x80 * (ev))



#define GSI_EV_CH_E_CNTXT_4_OFFSET(ev) \

			(0x0001d010 + 0x4000 * GSI_EE_AP + 0x80 * (ev))



#define GSI_EV_CH_E_CNTXT_8_OFFSET(ev) \

			(0x0001d020 + 0x4000 * GSI_EE_AP + 0x80 * (ev))

/* EV_CH_E_CNTXT_8 register */

#define MODT_FMASK			GENMASK(15, 0)

#define MODC_FMASK			GENMASK(23, 16)

#define MOD_CNT_FMASK			GENMASK(31, 24)



#define GSI_EV_CH_E_CNTXT_9_OFFSET(ev) \

			(0x0001d024 + 0x4000 * GSI_EE_AP + 0x80 * (ev))



#define GSI_EV_CH_E_CNTXT_10_OFFSET(ev) \

			(0x0001d028 + 0x4000 * GSI_EE_AP + 0x80 * (ev))



#define GSI_EV_CH_E_CNTXT_11_OFFSET(ev) \

			(0x0001d02c + 0x4000 * GSI_EE_AP + 0x80 * (ev))



#define GSI_EV_CH_E_CNTXT_12_OFFSET(ev) \

			(0x0001d030 + 0x4000 * GSI_EE_AP + 0x80 * (ev))



#define GSI_EV_CH_E_CNTXT_13_OFFSET(ev) \

			(0x0001d034 + 0x4000 * GSI_EE_AP + 0x80 * (ev))



#define GSI_EV_CH_E_SCRATCH_0_OFFSET(ev) \

			(0x0001d048 + 0x4000 * GSI_EE_AP + 0x80 * (ev))



#define GSI_EV_CH_E_SCRATCH_1_OFFSET(ev) \

			(0x0001d04c + 0x4000 * GSI_EE_AP + 0x80 * (ev))



#define GSI_CH_C_DOORBELL_0_OFFSET(ch) \

			(0x0001e000 + 0x4000 * GSI_EE_AP + 0x08 * (ch))



#define GSI_EV_CH_E_DOORBELL_0_OFFSET(ev) \

			(0x0001e100 + 0x4000 * GSI_EE_AP + 0x08 * (ev))



#define GSI_GSI_STATUS_OFFSET \

			(0x0001f000 + 0x4000 * GSI_EE_AP)

/* GSI_STATUS register */

#define ENABLED_FMASK			GENMASK(0, 0)



#define GSI_CH_CMD_OFFSET \

			(0x0001f008 + 0x4000 * GSI_EE_AP)

/* CH_CMD register */

#define CH_CHID_FMASK			GENMASK(7, 0)

#define CH_OPCODE_FMASK			GENMASK(31, 24)
@@ -204,8 +171,7 @@ enum gsi_ch_cmd_opcode { 
	GSI_CH_DB_STOP				= 0xb,

};



#define GSI_EV_CH_CMD_OFFSET \

			(0x0001f010 + 0x4000 * GSI_EE_AP)

/* EV_CH_CMD register */

#define EV_CHID_FMASK			GENMASK(7, 0)

#define EV_OPCODE_FMASK			GENMASK(31, 24)
@@ -216,8 +182,7 @@ enum gsi_evt_cmd_opcode { 
	GSI_EVT_DE_ALLOC			= 0xa,

};



#define GSI_GENERIC_CMD_OFFSET \

			(0x0001f018 + 0x4000 * GSI_EE_AP)

/* GENERIC_CMD register */

#define GENERIC_OPCODE_FMASK		GENMASK(4, 0)

#define GENERIC_CHID_FMASK		GENMASK(9, 5)

#define GENERIC_EE_FMASK		GENMASK(13, 10)
@@ -232,9 +197,7 @@ enum gsi_generic_cmd_opcode { 
	GSI_GENERIC_QUERY_FLOW_CONTROL		= 0x5,	/* IPA v4.11+ */

};



/* The next register is present for IPA v3.5.1 and above */

#define GSI_GSI_HW_PARAM_2_OFFSET \

			(0x0001f040 + 0x4000 * GSI_EE_AP)

/* HW_PARAM_2 register */				/* IPA v3.5.1+ */

#define IRAM_SIZE_FMASK			GENMASK(2, 0)

#define NUM_CH_PER_EE_FMASK		GENMASK(7, 3)

#define NUM_EV_PER_EE_FMASK		GENMASK(12, 8)
@@ -261,12 +224,6 @@ enum gsi_iram_size { 
	IRAM_SIZE_FOUR_KB			= 0x5,

};



/* IRQ condition for each type is cleared by writing type-specific register */

#define GSI_CNTXT_TYPE_IRQ_OFFSET \

			(0x0001f080 + 0x4000 * GSI_EE_AP)

#define GSI_CNTXT_TYPE_IRQ_MSK_OFFSET \

			(0x0001f088 + 0x4000 * GSI_EE_AP)



/**

 * enum gsi_irq_type_id: GSI IRQ types

 * @GSI_CH_CTRL:		Channel allocation, deallocation, etc.
@@ -288,40 +245,6 @@ enum gsi_irq_type_id { 
	/* IRQ types 7-31 (and their bit values) are reserved */

};



#define GSI_CNTXT_SRC_CH_IRQ_OFFSET \

			(0x0001f090 + 0x4000 * GSI_EE_AP)



#define GSI_CNTXT_SRC_EV_CH_IRQ_OFFSET \

			(0x0001f094 + 0x4000 * GSI_EE_AP)



#define GSI_CNTXT_SRC_CH_IRQ_MSK_OFFSET \

			(0x0001f098 + 0x4000 * GSI_EE_AP)



#define GSI_CNTXT_SRC_EV_CH_IRQ_MSK_OFFSET \

			(0x0001f09c + 0x4000 * GSI_EE_AP)



#define GSI_CNTXT_SRC_CH_IRQ_CLR_OFFSET \

			(0x0001f0a0 + 0x4000 * GSI_EE_AP)



#define GSI_CNTXT_SRC_EV_CH_IRQ_CLR_OFFSET \

			(0x0001f0a4 + 0x4000 * GSI_EE_AP)



#define GSI_CNTXT_SRC_IEOB_IRQ_OFFSET \

			(0x0001f0b0 + 0x4000 * GSI_EE_AP)



#define GSI_CNTXT_SRC_IEOB_IRQ_MSK_OFFSET \

			(0x0001f0b8 + 0x4000 * GSI_EE_AP)



#define GSI_CNTXT_SRC_IEOB_IRQ_CLR_OFFSET \

			(0x0001f0c0 + 0x4000 * GSI_EE_AP)



#define GSI_CNTXT_GLOB_IRQ_STTS_OFFSET \

			(0x0001f100 + 0x4000 * GSI_EE_AP)

#define GSI_CNTXT_GLOB_IRQ_EN_OFFSET \

			(0x0001f108 + 0x4000 * GSI_EE_AP)

#define GSI_CNTXT_GLOB_IRQ_CLR_OFFSET \

			(0x0001f110 + 0x4000 * GSI_EE_AP)



/** enum gsi_global_irq_id: Global GSI interrupt events */

enum gsi_global_irq_id {

	ERROR_INT				= BIT(0),
@@ -331,13 +254,6 @@ enum gsi_global_irq_id { 
	/* Global IRQ types 4-31 (and their bit values) are reserved */

};



#define GSI_CNTXT_GSI_IRQ_STTS_OFFSET \

			(0x0001f118 + 0x4000 * GSI_EE_AP)

#define GSI_CNTXT_GSI_IRQ_EN_OFFSET \

			(0x0001f120 + 0x4000 * GSI_EE_AP)

#define GSI_CNTXT_GSI_IRQ_CLR_OFFSET \

			(0x0001f128 + 0x4000 * GSI_EE_AP)



/** enum gsi_general_irq_id: GSI general IRQ conditions */

enum gsi_general_irq_id {

	BREAK_POINT				= BIT(0),
@@ -347,13 +263,10 @@ enum gsi_general_irq_id { 
	/* General IRQ types 4-31 (and their bit values) are reserved */

};



#define GSI_CNTXT_INTSET_OFFSET \

			(0x0001f180 + 0x4000 * GSI_EE_AP)

/* CNTXT_INTSET register */

#define INTYPE_FMASK			GENMASK(0, 0)



#define GSI_ERROR_LOG_OFFSET \

			(0x0001f200 + 0x4000 * GSI_EE_AP)



/* ERROR_LOG register */

#define ERR_ARG3_FMASK			GENMASK(3, 0)

#define ERR_ARG2_FMASK			GENMASK(7, 4)

#define ERR_ARG1_FMASK			GENMASK(11, 8)
@@ -381,11 +294,7 @@ enum gsi_err_type { 
	GSI_ERR_TYPE_EVT			= 0x3,

};



#define GSI_ERROR_LOG_CLR_OFFSET \

			(0x0001f210 + 0x4000 * GSI_EE_AP)



#define GSI_CNTXT_SCRATCH_0_OFFSET \

			(0x0001f400 + 0x4000 * GSI_EE_AP)

/* CNTXT_SCRATCH_0 register */

#define INTER_EE_RESULT_FMASK		GENMASK(2, 0)

#define GENERIC_EE_RESULT_FMASK		GENMASK(7, 5)
@@ -400,4 +309,31 @@ enum gsi_generic_ee_result { 
	GENERIC_EE_NO_RESOURCES			= 0x7,

};



extern const struct regs gsi_regs_v3_1;

extern const struct regs gsi_regs_v3_5_1;



/**

 * gsi_reg() - Return the structure describing a GSI register

 * @gsi:	GSI pointer

 * @reg_id:	GSI register ID

 */

const struct reg *gsi_reg(struct gsi *gsi, enum gsi_reg_id reg_id);



/**

 * gsi_reg_init() - Perform GSI register initialization

 * @gsi:	GSI pointer

 * @pdev:	GSI (IPA) platform device

 *

 * Initialize GSI registers, including looking up and I/O mapping

 * the "gsi" memory space.  This function sets gsi->virt_raw and

 * gsi->virt.

 */

int gsi_reg_init(struct gsi *gsi, struct platform_device *pdev);



/**

 * gsi_reg_exit() - Inverse of gsi_reg_init()

 * @gsi:	GSI pointer

 */

void gsi_reg_exit(struct gsi *gsi);



#endif	/* _GSI_REG_H_ */