Commit 8023d3be authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Nuke intel_dp_set_m_n() 



I want to make a clean split betwen the CPU vs. PCH transcoder
programming. To that end eliminate intel_dp_set_m_n() and just
call the individual CPU/PCH transcoder functions directly.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220128103757.22461-2-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
parent c50df701

drivers/gpu/drm/i915/display/intel_ddi.c

+3 −1
Original line number Diff line number Diff line
@@ -2510,7 +2510,9 @@ static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state, 
	if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST)) {

		intel_ddi_set_dp_msa(crtc_state, conn_state);



		intel_dp_set_m_n(crtc_state, M1_N1);

		intel_cpu_transcoder_set_m_n(crtc_state,

					     &crtc_state->dp_m_n,

					     &crtc_state->dp_m2_n2);

	}

}

drivers/gpu/drm/i915/display/intel_display.c

+20 −36
Original line number Diff line number Diff line
@@ -118,9 +118,8 @@ 


static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);

static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);

static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,

					 const struct intel_link_m_n *m_n,

					 const struct intel_link_m_n *m2_n2);

static void intel_pch_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,

					 const struct intel_link_m_n *m_n);

static void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state);

static void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state);

static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
@@ -1835,8 +1834,15 @@ static void ilk_crtc_enable(struct intel_atomic_state *state, 
	intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);

	intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);



	if (intel_crtc_has_dp_encoder(new_crtc_state))

		intel_dp_set_m_n(new_crtc_state, M1_N1);

	if (intel_crtc_has_dp_encoder(new_crtc_state)) {

		if (new_crtc_state->has_pch_encoder)

			intel_pch_transcoder_set_m_n(new_crtc_state,

						     &new_crtc_state->dp_m_n);

		else

			intel_cpu_transcoder_set_m_n(new_crtc_state,

						     &new_crtc_state->dp_m_n,

						     &new_crtc_state->dp_m2_n2);

	}



	intel_set_transcoder_timings(new_crtc_state);

	intel_set_pipe_src_size(new_crtc_state);
@@ -2450,7 +2456,9 @@ static void valleyview_crtc_enable(struct intel_atomic_state *state, 
		return;



	if (intel_crtc_has_dp_encoder(new_crtc_state))

		intel_dp_set_m_n(new_crtc_state, M1_N1);

		intel_cpu_transcoder_set_m_n(new_crtc_state,

					     &new_crtc_state->dp_m_n,

					     &new_crtc_state->dp_m2_n2);



	intel_set_transcoder_timings(new_crtc_state);

	intel_set_pipe_src_size(new_crtc_state);
@@ -2502,7 +2510,9 @@ static void i9xx_crtc_enable(struct intel_atomic_state *state, 
		return;



	if (intel_crtc_has_dp_encoder(new_crtc_state))

		intel_dp_set_m_n(new_crtc_state, M1_N1);

		intel_cpu_transcoder_set_m_n(new_crtc_state,

					     &new_crtc_state->dp_m_n,

					     &new_crtc_state->dp_m2_n2);



	intel_set_transcoder_timings(new_crtc_state);

	intel_set_pipe_src_size(new_crtc_state);
@@ -3149,7 +3159,7 @@ static bool transcoder_has_m2_n2(struct drm_i915_private *dev_priv, 
	return DISPLAY_VER(dev_priv) == 7 || IS_CHERRYVIEW(dev_priv);

}



static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,

void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,

				  const struct intel_link_m_n *m_n,

				  const struct intel_link_m_n *m2_n2)

{
@@ -3179,32 +3189,6 @@ static void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_sta 
	}

}



void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state, enum link_m_n_set m_n)

{

	const struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;

	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);



	if (m_n == M1_N1) {

		dp_m_n = &crtc_state->dp_m_n;

		dp_m2_n2 = &crtc_state->dp_m2_n2;

	} else if (m_n == M2_N2) {



		/*

		 * M2_N2 registers are not supported. Hence m2_n2 divider value

		 * needs to be programmed into M1_N1.

		 */

		dp_m_n = &crtc_state->dp_m2_n2;

	} else {

		drm_err(&i915->drm, "Unsupported divider value\n");

		return;

	}



	if (crtc_state->has_pch_encoder)

		intel_pch_transcoder_set_m_n(crtc_state, &crtc_state->dp_m_n);

	else

		intel_cpu_transcoder_set_m_n(crtc_state, dp_m_n, dp_m2_n2);

}



static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)

{

	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);

drivers/gpu/drm/i915/display/intel_display.h

+3 −3
Original line number Diff line number Diff line
@@ -27,7 +27,6 @@ 


#include <drm/drm_util.h>



enum link_m_n_set;

enum drm_scaling_filter;

struct dpll;

struct drm_connector;
@@ -607,8 +606,9 @@ void intel_display_prepare_reset(struct drm_i915_private *dev_priv); 
void intel_display_finish_reset(struct drm_i915_private *dev_priv);

void intel_dp_get_m_n(struct intel_crtc *crtc,

		      struct intel_crtc_state *pipe_config);

void intel_dp_set_m_n(const struct intel_crtc_state *crtc_state,

		      enum link_m_n_set m_n);

void intel_cpu_transcoder_set_m_n(const struct intel_crtc_state *crtc_state,

				  const struct intel_link_m_n *m_n,

				  const struct intel_link_m_n *m2_n2);

void ilk_get_fdi_m_n_config(struct intel_crtc *crtc,

			    struct intel_crtc_state *pipe_config);

void i9xx_crtc_clock_get(struct intel_crtc *crtc,

drivers/gpu/drm/i915/display/intel_display_types.h

+0 −19
Original line number Diff line number Diff line
@@ -1445,25 +1445,6 @@ struct intel_hdmi { 
};



struct intel_dp_mst_encoder;

/*

 * enum link_m_n_set:

 *	When platform provides two set of M_N registers for dp, we can

 *	program them and switch between them incase of DRRS.

 *	But When only one such register is provided, we have to program the

 *	required divider value on that registers itself based on the DRRS state.

 *

 * M1_N1	: Program dp_m_n on M1_N1 registers

 *			  dp_m2_n2 on M2_N2 registers (If supported)

 *

 * M2_N2	: Program dp_m2_n2 on M1_N1 registers

 *			  M2_N2 registers are not supported

 */



enum link_m_n_set {

	/* Sets the m1_n1 and m2_n2 */

	M1_N1 = 0,

	M2_N2

};



struct intel_dp_compliance_data {

	unsigned long edid;

drivers/gpu/drm/i915/display/intel_dp_mst.c

+3 −1
Original line number Diff line number Diff line
@@ -523,7 +523,9 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, 


	intel_ddi_set_dp_msa(pipe_config, conn_state);



	intel_dp_set_m_n(pipe_config, M1_N1);

	intel_cpu_transcoder_set_m_n(pipe_config,

				     &pipe_config->dp_m_n,

				     &pipe_config->dp_m2_n2);

}



static void intel_mst_enable_dp(struct intel_atomic_state *state,