Commit 80059b87 authored by Rob Clark's avatar Rob Clark
Browse files

drm/msm: De-open-code some CP_EVENT_WRITE 



Replace some open coding to improve readability.

Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/499272/
Link: https://lore.kernel.org/r/20220821155441.1092134-1-robdclark@gmail.com
parent 70bccecf

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -68,7 +68,7 @@ static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 


	/* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */

	OUT_PKT3(ring, CP_EVENT_WRITE, 3);

	OUT_RING(ring, CACHE_FLUSH_TS | BIT(31));

	OUT_RING(ring, CACHE_FLUSH_TS | CP_EVENT_WRITE_0_IRQ);

	OUT_RING(ring, rbmemptr(ring, fence));

	OUT_RING(ring, submit->seqno);

drivers/gpu/drm/msm/adreno/a4xx_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -62,7 +62,7 @@ static void a4xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit) 


	/* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */

	OUT_PKT3(ring, CP_EVENT_WRITE, 3);

	OUT_RING(ring, CACHE_FLUSH_TS | BIT(31));

	OUT_RING(ring, CACHE_FLUSH_TS | CP_EVENT_WRITE_0_IRQ);

	OUT_RING(ring, rbmemptr(ring, fence));

	OUT_RING(ring, submit->seqno);

drivers/gpu/drm/msm/adreno/a6xx_gpu.c

+1 −1
Original line number Diff line number Diff line
@@ -146,7 +146,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu, 
	 */



	OUT_PKT7(ring, CP_EVENT_WRITE, 1);

	OUT_RING(ring, 0x31);

	OUT_RING(ring, CACHE_INVALIDATE);



	if (!sysprof) {

		/*