powerpc/32s: Enhance readability of trap types (7fab6397) · Commits · EulixOS / Software / Kernel

arch/powerpc/include/asm/interrupt.h

+6 −0

Original line number	Diff line number	Diff line
		@@ -27,6 +27,7 @@
		#ifdef CONFIG_PPC_BOOK3S
		#define INTERRUPT_DOORBELL 0xa00
		#define INTERRUPT_PERFMON 0xf00
		#define INTERRUPT_ALTIVEC_UNAVAIL 0xf20
		#endif

		/* BookE/BookS/4xx/8xx */
		@@ -57,6 +58,11 @@
		#define INTERRUPT_DATA_BREAKPOINT_8xx 0x1c00
		#define INTERRUPT_INST_BREAKPOINT_8xx 0x1d00

		/* 603 */
		#define INTERRUPT_INST_TLB_MISS_603 0x1000
		#define INTERRUPT_DATA_LOAD_TLB_MISS_603 0x1100
		#define INTERRUPT_DATA_STORE_TLB_MISS_603 0x1200

		#ifndef __ASSEMBLY__

		#include <linux/context_tracking.h>

arch/powerpc/kernel/head_book3s_32.S

+22 −21

Original line number	Diff line number	Diff line
		@@ -31,6 +31,7 @@
		#include <asm/kvm_book3s_asm.h>
		#include <asm/export.h>
		#include <asm/feature-fixups.h>
		#include <asm/interrupt.h>

		#include "head_32.h"

		@@ -239,7 +240,7 @@ __secondary_hold_acknowledge:
		/* System reset */
		/* core99 pmac starts the seconary here by changing the vector, and
		putting it back to what it was (unknown_async_exception) when done. */
		EXCEPTION(0x100, Reset, unknown_async_exception)
		EXCEPTION(INTERRUPT_SYSTEM_RESET, Reset, unknown_async_exception)

		/* Machine check */
		/*
		@@ -255,7 +256,7 @@ __secondary_hold_acknowledge:
		* pointer when we take an exception from supervisor mode.)
		* -- paulus.
		*/
		START_EXCEPTION(0x200, MachineCheck)
		START_EXCEPTION(INTERRUPT_MACHINE_CHECK, MachineCheck)
		EXCEPTION_PROLOG_0
		#ifdef CONFIG_PPC_CHRP
		mtspr SPRN_SPRG_SCRATCH2,r1
		@@ -276,7 +277,7 @@ __secondary_hold_acknowledge:
		b interrupt_return

		/* Data access exception. */
		START_EXCEPTION(0x300, DataAccess)
		START_EXCEPTION(INTERRUPT_DATA_STORAGE, DataAccess)
		#ifdef CONFIG_PPC_BOOK3S_604
		BEGIN_MMU_FTR_SECTION
		mtspr SPRN_SPRG_SCRATCH2,r10
		@@ -297,7 +298,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)
		#endif
		1: EXCEPTION_PROLOG_0 handle_dar_dsisr=1
		EXCEPTION_PROLOG_1
		EXCEPTION_PROLOG_2 0x300 DataAccess handle_dar_dsisr=1
		EXCEPTION_PROLOG_2 INTERRUPT_DATA_STORAGE DataAccess handle_dar_dsisr=1
		prepare_transfer_to_handler
		lwz r5, _DSISR(r11)
		andis. r0, r5, DSISR_DABRMATCH@h
		@@ -310,7 +311,7 @@ ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_HPTE_TABLE)


		/* Instruction access exception. */
		START_EXCEPTION(0x400, InstructionAccess)
		START_EXCEPTION(INTERRUPT_INST_STORAGE, InstructionAccess)
		mtspr SPRN_SPRG_SCRATCH0,r10
		mtspr SPRN_SPRG_SCRATCH1,r11
		mfspr r10, SPRN_SPRG_THREAD
		@@ -330,7 +331,7 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
		andi. r11, r11, MSR_PR

		EXCEPTION_PROLOG_1
		EXCEPTION_PROLOG_2 0x400 InstructionAccess
		EXCEPTION_PROLOG_2 INTERRUPT_INST_STORAGE InstructionAccess
		andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
		stw r5, _DSISR(r11)
		stw r12, _DAR(r11)
		@@ -339,19 +340,19 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_HPTE_TABLE)
		b interrupt_return

		/* External interrupt */
		EXCEPTION(0x500, HardwareInterrupt, do_IRQ)
		EXCEPTION(INTERRUPT_EXTERNAL, HardwareInterrupt, do_IRQ)

		/* Alignment exception */
		START_EXCEPTION(0x600, Alignment)
		EXCEPTION_PROLOG 0x600 Alignment handle_dar_dsisr=1
		START_EXCEPTION(INTERRUPT_ALIGNMENT, Alignment)
		EXCEPTION_PROLOG INTERRUPT_ALIGNMENT Alignment handle_dar_dsisr=1
		prepare_transfer_to_handler
		bl alignment_exception
		REST_NVGPRS(r1)
		b interrupt_return

		/* Program check exception */
		START_EXCEPTION(0x700, ProgramCheck)
		EXCEPTION_PROLOG 0x700 ProgramCheck
		START_EXCEPTION(INTERRUPT_PROGRAM, ProgramCheck)
		EXCEPTION_PROLOG INTERRUPT_PROGRAM ProgramCheck
		prepare_transfer_to_handler
		bl program_check_exception
		REST_NVGPRS(r1)
		@@ -367,7 +368,7 @@ BEGIN_FTR_SECTION
		*/
		b ProgramCheck
		END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
		EXCEPTION_PROLOG 0x800 FPUnavailable
		EXCEPTION_PROLOG INTERRUPT_FP_UNAVAIL FPUnavailable
		beq 1f
		bl load_up_fpu /* if from user, just load it up */
		b fast_exception_return
		@@ -379,16 +380,16 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
		#endif

		/* Decrementer */
		EXCEPTION(0x900, Decrementer, timer_interrupt)
		EXCEPTION(INTERRUPT_DECREMENTER, Decrementer, timer_interrupt)

		EXCEPTION(0xa00, Trap_0a, unknown_exception)
		EXCEPTION(0xb00, Trap_0b, unknown_exception)

		/* System call */
		START_EXCEPTION(0xc00, SystemCall)
		SYSCALL_ENTRY 0xc00
		START_EXCEPTION(INTERRUPT_SYSCALL, SystemCall)
		SYSCALL_ENTRY INTERRUPT_SYSCALL

		EXCEPTION(0xd00, SingleStep, single_step_exception)
		EXCEPTION(INTERRUPT_TRACE, SingleStep, single_step_exception)
		EXCEPTION(0xe00, Trap_0e, unknown_exception)

		/*
		@@ -399,10 +400,10 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
		* non-altivec kernel running on a machine with altivec just
		* by executing an altivec instruction.
		*/
		START_EXCEPTION(0xf00, PerformanceMonitorTrap)
		START_EXCEPTION(INTERRUPT_PERFMON, PerformanceMonitorTrap)
		b PerformanceMonitor

		START_EXCEPTION(0xf20, AltiVecUnavailableTrap)
		START_EXCEPTION(INTERRUPT_ALTIVEC_UNAVAIL, AltiVecUnavailableTrap)
		b AltiVecUnavailable

		__HEAD
		@@ -410,7 +411,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_FPU_UNAVAILABLE)
		* Handle TLB miss for instruction on 603/603e.
		* Note: we get an alternate set of r0 - r3 to use automatically.
		*/
		. = 0x1000
		. = INTERRUPT_INST_TLB_MISS_603
		InstructionTLBMiss:
		/*
		* r0: scratch
		@@ -476,7 +477,7 @@ InstructionAddressInvalid:
		/*
		* Handle TLB miss for DATA Load operation on 603/603e
		*/
		. = 0x1100
		. = INTERRUPT_DATA_LOAD_TLB_MISS_603
		DataLoadTLBMiss:
		/*
		* r0: scratch
		@@ -554,7 +555,7 @@ DataAddressInvalid:
		/*
		* Handle TLB miss for DATA Store on 603/603e
		*/
		. = 0x1200
		. = INTERRUPT_DATA_STORE_TLB_MISS_603
		DataStoreTLBMiss:
		/*
		* r0: scratch