Commit 7ece3cbc authored by Philippe Schenker's avatar Philippe Schenker Committed by Shawn Guo
Browse files

arm64: dts: colibri-imx8x: Add atmel pinctrl groups 



Add pinctrl groups for enabling atmel touchscreen support.
Remove the pads out of pinctrl_hog0 as they now can be enabled more
specific using pinctrl_atmel_conn label.

Signed-off-by: default avatarPhilippe Schenker <philippe.schenker@toradex.com>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 7efa409e

arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi

+17 −3
Original line number Diff line number Diff line
@@ -134,6 +134,22 @@ 
			   <IMX8QXP_ADC_IN5_ADMA_ADC_IN5			0x60>;		/* SODIMM   2 */

	};



	/* Atmel MXT touchsceen + Capacitive Touch Adapter */

	/* NOTE: This pingroup conflicts with pingroups

	 * pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them

	 * simultaneously.

	 */

	pinctrl_atmel_adap: atmeladaptergrp {

		fsl,pins = <IMX8QXP_UART1_RX_LSIO_GPIO0_IO22			0x21>,		/* SODIMM  30 */

			   <IMX8QXP_UART1_TX_LSIO_GPIO0_IO21			0x4000021>;	/* SODIMM  28 */

	};



	/* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */

	pinctrl_atmel_conn: atmelconnectorgrp {

		fsl,pins = <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20		0x4000021>,	/* SODIMM 107 */

			   <IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24		0x21>;		/* SODIMM 106 */

	};



	pinctrl_can_int: canintgrp {

		fsl,pins = <IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13			0x40>;		/* SODIMM  73 */

	};
@@ -218,7 +234,6 @@ 
			   <IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25			0x20>,		/* SODIMM 103 */

			   <IMX8QXP_CSI_D01_CI_PI_D03				0x61>,		/* SODIMM 103 */

			   <IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19		0x20>,		/* SODIMM 105 */

			   <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20		0x20>,		/* SODIMM 107 */

			   <IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05			0x20>,		/* SODIMM 127 */

			   <IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06			0x20>,		/* SODIMM 131 */

			   <IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04			0x20>,		/* SODIMM 133 */
@@ -226,8 +241,7 @@ 
			   <IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21		0x20>,		/* SODIMM  98 */

			   <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31			0x20>,		/* SODIMM 100 */

			   <IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22			0x20>,		/* SODIMM 102 */

			   <IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23		0x20>,		/* SODIMM 104 */

			   <IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24		0x20>;		/* SODIMM 106 */

			   <IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23		0x20>;		/* SODIMM 104 */

	};



	pinctrl_hog1: hog1grp {