Commit 7eac0081 authored by Conor Dooley's avatar Conor Dooley
Browse files

riscv: dts: microchip: add qspi compatible fallback 

The "hard" QSPI peripheral on PolarFire SoC is derived from version 2
of the FPGA IP core. The original binding had no fallback etc, so this
device tree is valid as is. There was also no functional driver for the
QSPI IP, so no device with a devicetree from a previous mainline
release will regress.

Link: https://lore.kernel.org/linux-spi/7c9f0d96-2882-964a-cd1f-916ddb3f0410@linaro.org/


Signed-off-by: default avatarConor Dooley <conor.dooley@microchip.com>
Acked-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 69dac8e4

arch/riscv/boot/dts/microchip/mpfs.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -330,7 +330,7 @@ 
		};



		qspi: spi@21000000 {

			compatible = "microchip,mpfs-qspi";

			compatible = "microchip,mpfs-qspi", "microchip,coreqspi-rtl-v2";

			#address-cells = <1>;

			#size-cells = <0>;

			reg = <0x0 0x21000000 0x0 0x1000>;