Unverified Commit 7ea5a736 authored by Andrew Jones's avatar Andrew Jones Committed by Palmer Dabbelt
Browse files

RISC-V: Add Zicboz detection and block size parsing 



Parse "riscv,cboz-block-size" from the DT by piggybacking on Zicbom's
riscv_init_cbom_blocksize(). Additionally check the DT for the presence
of the "zicboz" extension and, when it's present, validate the parsed
cboz block size as we do Zicbom's cbom block size with
riscv_isa_extension_check().

Signed-off-by: default avatarAndrew Jones <ajones@ventanamicro.com>
Reviewed-by: default avatarHeiko Stuebner <heiko@sntech.de>
Reviewed-by: default avatarConor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20230224162631.405473-5-ajones@ventanamicro.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent ea20f117

arch/riscv/include/asm/cacheflush.h

+2 −1
Original line number Diff line number Diff line
@@ -50,7 +50,8 @@ void flush_icache_mm(struct mm_struct *mm, bool local); 
#endif /* CONFIG_SMP */



extern unsigned int riscv_cbom_block_size;

void riscv_init_cbom_blocksize(void);

extern unsigned int riscv_cboz_block_size;

void riscv_init_cbo_blocksizes(void);



#ifdef CONFIG_RISCV_DMA_NONCOHERENT

void riscv_noncoherent_supported(void);

arch/riscv/include/asm/hwcap.h

+1 −0
Original line number Diff line number Diff line
@@ -42,6 +42,7 @@ 
#define RISCV_ISA_EXT_ZBB		30

#define RISCV_ISA_EXT_ZICBOM		31

#define RISCV_ISA_EXT_ZIHINTPAUSE	32

#define RISCV_ISA_EXT_ZICBOZ		33



#define RISCV_ISA_EXT_MAX		64

#define RISCV_ISA_EXT_NAME_LEN_MAX	32

arch/riscv/kernel/cpu.c

+1 −0
Original line number Diff line number Diff line
@@ -186,6 +186,7 @@ arch_initcall(riscv_cpuinfo_init); 
 */

static struct riscv_isa_ext_data isa_ext_arr[] = {

	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),

	__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),

	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),

	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),

	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),

arch/riscv/kernel/cpufeature.c

+10 −0
Original line number Diff line number Diff line
@@ -74,6 +74,15 @@ static bool riscv_isa_extension_check(int id) 
			return false;

		}

		return true;

	case RISCV_ISA_EXT_ZICBOZ:

		if (!riscv_cboz_block_size) {

			pr_err("Zicboz detected in ISA string, but no cboz-block-size found\n");

			return false;

		} else if (!is_power_of_2(riscv_cboz_block_size)) {

			pr_err("cboz-block-size present, but is not a power-of-2\n");

			return false;

		}

		return true;

	}



	return true;
@@ -222,6 +231,7 @@ void __init riscv_fill_hwcap(void) 
				SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);

				SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);

				SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);

				SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);

				SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE);

			}

#undef SET_ISA_EXT_MAP

arch/riscv/kernel/setup.c

+1 −1
Original line number Diff line number Diff line
@@ -297,7 +297,7 @@ void __init setup_arch(char **cmdline_p) 
	setup_smp();

#endif



	riscv_init_cbom_blocksize();

	riscv_init_cbo_blocksizes();

	riscv_fill_hwcap();

	apply_boot_alternatives();

	if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&