Commit 7e6ee553 authored by Krishna Manikandan's avatar Krishna Manikandan Committed by Rob Clark
Browse files

drm/msm/disp/dpu1: enable DATA_HCTL_EN for sc7280 target 



The reset value of INTF_CONFIG2 register is changed
for SC7280 family. Changes are added to program
this register correctly based on the target.

DATA_HCTL_EN in INTF_CONFIG2 register allows data
to be transferred at a different rate than video
timing. When this is set, the number of data per
line follows DISPLAY_DATA_HCTL register value.
This change adds support to program these
registers for sc7280 target.

Signed-off-by: default avatarKrishna Manikandan <mkrishn@codeaurora.org>
Link: https://lore.kernel.org/r/1617685792-14376-5-git-send-email-mkrishn@codeaurora.org


Signed-off-by: default avatarRob Clark <robdclark@chromium.org>
parent b3652e87

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c

+10 −1
Original line number Diff line number Diff line
@@ -31,6 +31,8 @@ 
#define INTF_TEST_CTL                   0x054

#define INTF_TP_COLOR0                  0x058

#define INTF_TP_COLOR1                  0x05C

#define INTF_CONFIG2                    0x060

#define INTF_DISPLAY_DATA_HCTL          0x064

#define INTF_FRAME_LINE_COUNT_EN        0x0A8

#define INTF_FRAME_COUNT                0x0AC

#define   INTF_LINE_COUNT               0x0B0
@@ -93,7 +95,7 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, 
	u32 active_hctl, display_hctl, hsync_ctl;

	u32 polarity_ctl, den_polarity, hsync_polarity, vsync_polarity;

	u32 panel_format;

	u32 intf_cfg;

	u32 intf_cfg, intf_cfg2 = 0, display_data_hctl = 0;



	/* read interface_cfg */

	intf_cfg = DPU_REG_READ(c, INTF_CONFIG);
@@ -178,6 +180,13 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, 
				(COLOR_8BIT << 4) |

				(0x21 << 8));



	if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) {

		intf_cfg2 |= BIT(4);

		display_data_hctl = display_hctl;

		DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2);

		DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl);

	}



	DPU_REG_WRITE(c, INTF_HSYNC_CTL, hsync_ctl);

	DPU_REG_WRITE(c, INTF_VSYNC_PERIOD_F0, vsync_period * hsync_period);

	DPU_REG_WRITE(c, INTF_VSYNC_PULSE_WIDTH_F0,