Unverified Commit 7e606eda authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'mvebu-fixes-5.17-2' of...

Merge tag 'mvebu-fixes-5.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/fixes

mvebu fixes for 5.17 (part 2)

Allow using old PCIe card on Armada 37xx

* tag 'mvebu-fixes-5.17-2' of git://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu:
  arm64: dts: marvell: armada-37xx: Remap IO space to bus address 0x0

Link: https://lore.kernel.org/r/87bkydj4fn.fsf@BL-laptop


Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents d986afd5 a1cc1697
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+6 −1
Original line number Diff line number Diff line
@@ -139,7 +139,9 @@
	/*
	 * U-Boot port for Turris Mox has a bug which always expects that "ranges" DT property
	 * contains exactly 2 ranges with 3 (child) address cells, 2 (parent) address cells and
	 * 2 size cells and also expects that the second range starts at 16 MB offset. If these
	 * 2 size cells and also expects that the second range starts at 16 MB offset. Also it
	 * expects that first range uses same address for PCI (child) and CPU (parent) cells (so
	 * no remapping) and that this address is the lowest from all specified ranges. If these
	 * conditions are not met then U-Boot crashes during loading kernel DTB file. PCIe address
	 * space is 128 MB long, so the best split between MEM and IO is to use fixed 16 MB window
	 * for IO and the rest 112 MB (64+32+16) for MEM, despite that maximal IO size is just 64 kB.
@@ -148,6 +150,9 @@
	 * https://source.denx.de/u-boot/u-boot/-/commit/cb2ddb291ee6fcbddd6d8f4ff49089dfe580f5d7
	 * https://source.denx.de/u-boot/u-boot/-/commit/c64ac3b3185aeb3846297ad7391fc6df8ecd73bf
	 * https://source.denx.de/u-boot/u-boot/-/commit/4a82fca8e330157081fc132a591ebd99ba02ee33
	 * Bug related to requirement of same child and parent addresses for first range is fixed
	 * in U-Boot version 2022.04 by following commit:
	 * https://source.denx.de/u-boot/u-boot/-/commit/1fd54253bca7d43d046bba4853fe5fafd034bc17
	 */
	#address-cells = <3>;
	#size-cells = <2>;
+1 −1
Original line number Diff line number Diff line
@@ -499,7 +499,7 @@
			 * (totaling 127 MiB) for MEM.
			 */
			ranges = <0x82000000 0 0xe8000000   0 0xe8000000   0 0x07f00000   /* Port 0 MEM */
				  0x81000000 0 0xefff0000   0 0xefff0000   0 0x00010000>; /* Port 0 IO */
				  0x81000000 0 0x00000000   0 0xefff0000   0 0x00010000>; /* Port 0 IO */
			interrupt-map-mask = <0 0 0 7>;
			interrupt-map = <0 0 0 1 &pcie_intc 0>,
					<0 0 0 2 &pcie_intc 1>,